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標題: | 第一型鎖相迴路之頻寬校正與次諧波注入鎖定技術 Type-I PLLs with Bandwidth Calibration and Subharmonically Injection-locked Technique |
作者: | Ming-Han Chou 周明翰 |
指導教授: | 劉深淵(Shen-Iuan Liu) |
關鍵字: | 鎖相迴路,第一型,閉迴路頻寬校正,次諧波注入鎖定, phase-locked loop,type-I,closed-loop bandwidth calibration,subharmonically injectionlocked, |
出版年 : | 2020 |
學位: | 碩士 |
摘要: | 本論文的主題為第一型鎖相迴路的頻寬校正及相位雜訊的改善。第一個部分實現了一個具前景迴路頻寬校正之第一型鎖相迴路,其利用循續漸近法,並透過數位調整主僕採樣濾波器的開關尺寸以校正迴路頻寬。此電路使用45 nm CMOS製程,面積為0.013 mm2。在輸出為2.4 GHz且供應電壓為0.9 V下,功率消耗為3.6 mW。積分範圍從1 kHz到100 MHz的方均根抖動量為3.6 ps。當使用所提出的頻寬校正方法,可以將迴路頻寬的變異從18.7%降低至4.6%。 第二部分實現了一個省面積、快速鎖定之注入鎖定第一型鎖相迴路。一個時間調整鑒相器被提出並用以校正注入時間,此時間調整鑒相器亦降低注入鎖定第一型鎖相迴路之鎖定時間。因為第一型鎖相迴路的迴路濾波器較小,故可達到小面積。此電路使用45 nm CMOS製程,面積為0.013 mm2。在輸出為2.4 GHz且供應電壓為0.87 V下,功率消耗為5.6 mW。積分範圍從1 kHz到40 MHz的方均根抖動量為0.91 ps。 This thesis which consists of two parts is based on the loop bandwidth calibration and the phase noise performance improvement of the type-I PLLs. The first part implements a type-I PLL with foreground loop bandwidth calibration. A successive approximation method is presented to calibrate the loop bandwidth by digitally adjusting the switch size of the master-slave sampling filter. This work is fabricated in 45 nm CMOS technology. Its active area is 0.013 mm2. The power consumption is 3.6 mW at 2.4 GHz for a supply of 0.9 V. The integrated jitter over 1 kHz to 100 MHz is 3.6 ps. By using the proposed loop bandwidth calibration, the variation of the loop bandwidth is reduced from 18.7% to 4.6%. The second part implements an area-efficient and fast-locking subharmonically injection-locked type-I PLL (SIL-TPLL). A timing-adjusted phase detector (TPD) is proposed to calibrate the injection timing. This TPD also reduces the settling time of the SIL-TPLL. The loop capacitance of the type-I PLL is tiny to save the area. This SIL-TPLL is fabricated in 45 nm CMOS technology. Its active area is 0.013 mm2. The power consumption is 5.6 mW at 2.4 GHz for a supply of 0.87 V. The integrated jitter of the SIL-TPLL over 1 kHz to 40 MHz is 0.91ps. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15484 |
DOI: | 10.6342/NTU202001583 |
全文授權: | 未授權 |
顯示於系所單位: | 電子工程學研究所 |
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U0001-1707202004540900.pdf 目前未授權公開取用 | 2.19 MB | Adobe PDF |
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