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標題: | 使用電容放大技術的0.0091mm^2孔徑雙重取樣鎖相迴路
A 0.0091mm^2 Aperture Double-Sampling Phase-Locked Loop with Capacitor Multiplier Technology |
作者: | Cheng-Hsien Huang 黃政憲 |
指導教授: | 陳中平(CHUNG-PING CHEN) |
關鍵字: | NULL |
出版年 : | 2020 |
學位: | 碩士 |
摘要: | 本論文為一個縫隙雙重取樣之鎖相迴路並採用電容放大技術。在現今5G通訊與穿戴式裝置技術快速的進步下,負責提供參考頻率的鎖相迴路必須朝著小面積、低雜訊的方向努力。然而,鎖相迴路中的低通濾波器往往由被動元件組成,因此佔據了很大的面積。此外,鎖相迴路中的充電汞會因為電流注入和電流分享的效應產生嚴重的參考突波,進而影響鎖相迴路的效能。 本篇論文為了解決上述提及的問題,討論並且提出了解決的辦法。首先,我們使用了電容放大技術,將原本佔據很大面積的低通濾波器,縮小了大約85%的面積。接著,我們使用了一個擁有三個運算放大器的緩衝充電汞,用來減少電流注入與電流分享的效應。最後,為了降低相位雜訊,本篇論文採用縫隙取樣技術,在參考訊號和除頻器輸出的頻率相同且相位差小於180度時,會關閉增益較低的頻率/相位偵測器,改用增益較高的縫隙取樣來鎖相,並且在縫隙取樣時,在每個參考頻率下比較相位兩次,因此在迴路關掉除頻器的同時,將其貢獻的相位雜訊降低至N^2/4,並同時降低參考突波。 本晶片使用台積電90奈米標準CMOS製程,晶片的主動面積為0.0091mm2,供應電壓為1.2V,參考頻率為93.75 MHz,震盪頻率為3 GHz,參考突波為-51dBc,在位移1MHz的相位雜訊為-93 dBc/Hz,方均根的抖動量是1.52ps,峰對峰的抖動量為2.86ps,功率消耗為10.8 mW。 This thesis is an aperture double-sampling phase-locked loop with capacitor multiplier technology. With the rapid progress of today’s 5G communication and wearable device technology, phase-locked loop responsible for providing the reference frequency must work towards the small area, and low noise. However, the low-pass filter occupies a large space in phase-locked loop, because it consists of passive components, whose area are large. Moreover, the charge pump in phase-locked loop will generate a serious reference spur due to the effects of charge injection and charge sharing, and affect the performance of the phase-locked loop. To solve the problems mentioned above, this thesis discusses and proposes solutions. First, we used capacitor multiplier technology to reduce the area about 85% of the low-pass filter that originally occupied a large area. Secondly, we used a buffered charge pump with three operational amplifiers to reduce the effects of charge injection and charge sharing. Finally, to reduce phase noise, this thesis uses aperture double-sampling technology. When the frequency of the reference signal and that of the divider output are the same and the phase difference is less than 180 degrees, the frequency / phase detector with lower gain will be turned off. The loop with higher-gain aperture sampling is used to phase lock, and compared the phase twice in each reference period during aperture sampling, so the phase noise contributed by the frequency divider is eliminated, APD/PAC/CP noise becomes N^2/4 times the original while it is turned off, and the reference spur can be scaled down. This chip is fabricated in TSMC 90nm standard CMOS technology. The active area of the chip is 0.0091mm2. The supply voltage is 1.2V. The reference frequency is 93.75 MHz. The oscillation frequency is 3 GHz. The reference spur is -51 dBc. The phase noise at 1MHz shift is -93 dBc / Hz. The rms jitter is 1.52 ps. The peak-to-peak jitter is 2.86 ps. The power consumption is 10.8 mW. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15352 |
DOI: | 10.6342/NTU202001181 |
全文授權: | 未授權 |
顯示於系所單位: | 電子工程學研究所 |
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U0001-2906202011232500.pdf 目前未授權公開取用 | 4.52 MB | Adobe PDF |
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