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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 王暉(Huei Wang) | |
dc.contributor.author | TAI-YU KUO | en |
dc.contributor.author | 郭岱宥 | zh_TW |
dc.date.accessioned | 2021-06-07T17:29:06Z | - |
dc.date.copyright | 2020-02-18 | |
dc.date.issued | 2020 | |
dc.date.submitted | 2020-02-13 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15263 | - |
dc.description.abstract | 本論文提出製作於65奈米互補式金屬氧化物半導體製程(CMOS FET)之可變增益放大器(VGA)以及同相與一個由90度相移分量升頻器(I/Q up-converter)及A類功率放大器所組成之發射機,此兩個設計皆應用於第五代行動通訊38 GHz頻段。
第二章首先介紹了兩級使用穩定中和技術(neutralization)的差動放大器搭配了電阻性負回授(resistive feedback)電路來達成增益控制的可變增益放大器,此可變增益放大器特點為在不同增益狀態下的輸出功率增益一分貝壓縮點(OP1dB)都大於8 dBm,且在頻率3-dB頻寬內之雜訊指數(NF)均保持在4 dB左右。而在38 GHz頻率點此可變增益放大器之增益控制範圍達到了9.2 dB,輸出功率增益壓縮一分貝點則保持在7.85到10 dBm之間,另外直流功耗則有88 mW。此一晶片之面積為0.4mm2。 第三章的部分則首先介紹了使用分離疊接架構(splitting cascode)之轉導級加上被動混頻器之升頻混頻器(Mixer),此一混頻器利用分離疊接架構來改善三階交互調變失真,在射頻頻率這個升頻混頻器之轉換增益為-1 dB,而雙頻量測(two-tone measurement)則顯示出在輸入功率約-13 dBm時有一個甜蜜點(sweet spot),此一晶片之面積為0.38毫米平方。基於升頻混頻器之架構上另外組成了同相與90度相移分量升頻器(I/Q up-converter),此一升頻器由兩個完全相同之升頻混頻器組成,在輸出端則接上了功率放大器用以放大射頻端之訊號。此一發射機在射頻頻率為40 GHz擁有25.5 dB之轉換增益,鏡像拒斥比則有20 dB,局部震盪洩漏(LO Leakage)達到了36 dB。雙頻量測展示了兩個甜蜜點,與模擬結果相符合,調變訊號量測結果顯示此一發射機最高可傳輸之資料傳輸速率為1.8 Gb/s,發射機的直流功耗為154.4 mW,晶片整體面積為1.03 mm2。 | zh_TW |
dc.description.abstract | This thesis proposed a variable-gain amplifier and a transmitter composed of an I/Q up-converter and a class-A power amplifier. Both designs aim for the fifth-generation mobile networks at the frequency band of 38 GHz.
In chapter 2, a VGA composed of two stages of differential amplifiers using neutralization technique and resistive feedback network to achieve gain control mechanism is proposed. The characteristic of this VGA is that the variation of the OP1dB under all gain states is above 8 dBm. Besides, within 3-dB bandwidth the noise figure is maintained around 4 dB. At 38 GHz, the gain control range is 9.2 dB. The OP1dB is from 7.85 to 10 dBm. The dc power consumption is 88 mW. The total chip size is 0.4 mm2. In chapter 3, the splitting cascode is realized at the transconductance stage and the mixer core is a passive mixer. The proposed mixer is applied to improve 3rd order intermodulation distortion. At RF frequency band of 39.5 to 40.7 GHz, the highest conversion gain of the mixer is -1 dB. The two-tone measurement results reveal that one sweet-spot occurs at input power of -13 dBm. The total chip size is 0.38 mm2. Based on this single mixer, the transmitter is composed of two mixers and a class-A power amplifier. The proposed transmitter exhibits 25.5 dB of conversion gain and the image rejection ratio (IRR) is 20 dB. The LO leakage of the transmitter achieves 36 dB. The two-tone measurement results reveal two sweet-spots, which agrees well with the simulation results. The modulated singal measurement shows that the highest data rate is 1.8 Gb/s. The dc power consumption of the transmitter is 154.4 mW and the chip area is 1.03 mm2. | en |
dc.description.provenance | Made available in DSpace on 2021-06-07T17:29:06Z (GMT). No. of bitstreams: 1 ntu-109-R05942146-1.pdf: 5443083 bytes, checksum: 10fe61812eb1907b2795159bbd74b767 (MD5) Previous issue date: 2020 | en |
dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vi LIST OF TABLES xiv Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Literature Survey 2 1.2.1 Variable Gain Amplifier 2 1.2.2 Transmitter with I/Q Up-Converter and Class-A Power Amplifier 5 1.3 Contributions 7 1.4 Thesis Organization 9 Chapter 2 A 31.7 to 39.2-GHz Variable Gain Amplifier in 65-nm CMOS Technology with Slight OP1dB and Noise Figure Variation. 10 2.1 Circuit Implementation 11 2.1.1 The Design of the Amplifier 13 2.1.2 Gain Control Circuit 30 2.2 Experimental Results and Discussion 46 2.3 Summary 57 Chapter 3 A 40-GHz High Linearity Transmitter in 65-nm CMOS Technology with 32-dBm OIP3 59 3.1 Introduction 59 3.1.1 3rd Order Intermodulation Distortion (IM3) 59 3.2 Circuit Design 62 3.2.1 High Linearity Up-Conversion Mixer 63 3.2.2 The Design of the Passive Mixer Core 65 3.2.3 The Design of the Transconductance Stage 69 3.2.4 The LC Tank at the Output of the Transconductance Stage 76 3.2.5 The Marchand Balun of the RF and LO ports 77 3.2.6 The Measurement Result of the Up-Conversion Mixer 81 3.2.7 The I/Q Up-converter [35] 83 3.2.8 Simulation Results 89 3.3 Experiment Results 92 3.4 Summary 102 Chapter 4 Conclusions 104 REFERENCE 106 | |
dc.language.iso | zh-TW | |
dc.title | 應用於5G無線系統之毫米波65奈米CMOS之可變增益放大器及發射機 | zh_TW |
dc.title | Design of Millimeter-Wave VGA and Transmitter in 65-nm CMOS Technology for 5G Application | en |
dc.type | Thesis | |
dc.date.schoolyear | 108-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃天偉,章朝盛,蔡作敏,林坤佑 | |
dc.subject.keyword | 第五代行動通訊,互補式金屬氧化物半導體製程,可變增益放大器,混頻器,發射機, | zh_TW |
dc.subject.keyword | 5G,CMOS,VGA,Mixer,Transmitter, | en |
dc.relation.page | 108 | |
dc.identifier.doi | 10.6342/NTU202000463 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2020-02-14 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
顯示於系所單位: | 電信工程學研究所 |
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