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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
| dc.contributor.author | Yong-Ru Lu | en |
| dc.contributor.author | 呂咏儒 | zh_TW |
| dc.date.accessioned | 2021-06-07T17:28:35Z | - |
| dc.date.copyright | 2020-06-09 | |
| dc.date.issued | 2020 | |
| dc.date.submitted | 2020-05-15 | |
| dc.identifier.citation | Y. Akamine, M. Kawabe, K. Hori, T. Okazaki, M. Kasahara and S. Tanaka, 'ΔΣ PLL transmitter with a loop-bandwidth calibration system,' IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 497-506, Feb. 2008.
H. Sun, K. Sobue, K. Hamashita, T. Anand and U. Moon, 'A 951-fsrms period jitter 3.2% modulation range in-band modulation spread-spectrum clock generator,' IEEE Journal of Solid-State Circuits, vol. 55, no. 2, pp. 426-438, Feb. 2020. T. Ebuchi, Y. Komatsu, T. Okamoto, Y. Arima, Y. Yamada, K. Sogawa, K. Okamoto, T. Morie, T. Hirata, S. Dosho and T. Yoshikawa, 'A 125–1250 MHz process-independent adaptive bandwidth spread spectrum clock generator with digital controlled Self-Calibration,' IEEE Journal of Solid-State Circuits, vol. 44, no. 3, pp. 763-774, Mar. 2009. T. Wu, P. K. Hanumolu, K. Mayaram and U. Moon, 'Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers,' IEEE Journal of Solid-State Circuits, vol. 44, no. 2, pp. 427-435, Feb. 2009. D. M. Fischett, A. L. S. Loke, R. J. DeSantis and G. R. Talbot, 'An embedded all-digital circuit to measure PLL response,' IEEE Journal of Solid-State Circuits, vol. 45, no. 8, pp. 1492-1503, Aug. 2010. J. Shin and H. Shin, 'A 1.9–3.8 GHz ΔΣ fractional-N PLL frequency synthesizer with fast auto-calibration of loop bandwidth and VCO frequency,' IEEE Journal of Solid-State Circuits, vol. 47, no. 3, pp. 665-675, Mar. 2012. A. Joshi and G. Midha, 'Bandwidth compensation technique for digital PLL,' IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 11, pp. 1044-1048, Nov. 2016. X. Gao, E. A. M. Klumperink, M. Bohsali and B. Nauta, 'A low noise sub-sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by N2,' IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3253-3263, Dec. 2009. D. Liao, F. F. Dai, B. Nauta and E. A. M. Klumperink, 'A 2.4-GHz 16-phase sub-sampling fractional-N PLL with robust soft loop switching,' IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 715-727, Mar. 2018. D. Liao, R. Wang and F. F. Dai, 'A low-noise inductor-less fractional-N sub-sampling PLL with multi-ring oscillator,' 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Honolulu, HI, June 2017, pp. 108-111. S. Bae, G. Kim and C. Kim, 'A 5-GHz subsampling PLL-based spread-spectrum clock generator by calibrating the frequency deviation,' IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 10, pp. 1132-1136, Oct. 2017. J. Chuang and H. Krishnaswamy, '19.4 A 0.0049mm2 2.3GHz sub-sampling ring-oscillator PLL with time-based loop filter achieving −236.2dB jitter-FOM,' 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2017, pp. 328-329. K. Raczkowski, N. Markulic, B. Hershberg and J. Craninckx, 'A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28 nm CMOS with 280 fs RMS jitter,' IEEE Journal of Solid-State Circuits, vol. 50, no. 5, pp. 1203-1213, May 2015. B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001 A. D. Berny, A. M. Niknejad and R. G. Meyer, 'A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration,' IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 909-917, Apr. 2005. R. G. Meyer, “Low-power monolithic RF peak detector analysis,” IEEE Journal of Solid-State Circuits, vol. 30, no. 1, pp. 65–67, Jan. 1995. B. Razavi, 'The StrongARM latch [A circuit for all seasons],' IEEE Solid-State Circuits Magazine, vol. 7, no. 2, pp. 12-17, Spring 2015. J. Shin and H. Shin, “A fast and high-precision VCO frequency calibration technique for wideband fractional-N frequency synthesizers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 7, pp. 1573–1582, July 2010. C. S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli and Z. Wang, 'A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology,' IEEE Journal of Solid-State Circuits, vol. 35, no. 7, pp. 1039-1045, July 2000. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15214 | - |
| dc.description.abstract | 本論文實現一個使用迴路頻寬校正降低製程變異的2.4-3.0十億赫茲次取樣鎖相迴路，藉由增益控制次取樣相位偵測器與脈衝寬度控制電路，迴路頻寬校正電路可以降低次取樣鎖相迴路對製程的變異，此外，論文中也分析了次取樣鎖相迴路的頻寬與電路參數間的關係，此次取樣鎖相迴路使用台積電40奈米CMOS製程製作且其面積約為0.15 mm2。在供應電壓為1.1 V下，其整體功率消耗為5.81 mW，參考頻率為75 MHz，輸出頻率範圍為2.4-3.0GHz。在輸出頻率為3.0GHz時，量測的方均根抖動量為2.02ps，迴路頻寬校正後，在輸出頻率為3.0GHz，與3.5MHz相比較，五顆晶片的最大迴路頻寬偏差可以從-71.4%減少為-18.5%。 | zh_TW |
| dc.description.abstract | In this thesis, a sub-sampling phase-locked loop (SSPLL) with loop bandwidth is presented. By using a sub-sampling phase detector with gain calibration and a pulse width control circuit, the loop bandwidth deviation of the SSPLL can be relaxed. This SSPLL is fabricated in a 40 nm CMOS process and its core area is 0.15mm2. The power consumption of the SSPLL is 5.81mW from a supply of 1.1V. The reference frequency is 75MHz and the output frequency tuning range is 2.4~3.0GHz. The measured rms jitter is 2.02ps at the output frequency of 3.0GHz. With the calibration, the largest loop bandwidth deviation from 3.5MHz among five samples is reduced from -71.4% to -18.5% at 3.0GHz. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-07T17:28:35Z (GMT). No. of bitstreams: 1 ntu-109-R05943008-1.pdf: 4911787 bytes, checksum: cd2db058158d65b438d43eae974461be (MD5) Previous issue date: 2020 | en |
| dc.description.tableofcontents | 1. Introduction…………………………………………………………. 1
1.1 Motivation………………………………………………….... 1 1.2 Overview……………………………………………………... 2 2. Previous Research………………………………………………….. 3 2.1 Review of the Sub-sampling PLL…………………………… 3 2.2 Review of the Loop Bandwidth Calibration………………… 4 3. Sub-sampling PLL Frequency Synthesizer with Bandwidth Calibration……………………………………………. 6 3.1 The SSPD Gain and Unity-gain Frequency of SSPLL……… 6 3.2 Circuit Description…………………………………………... 8 3.2.1 Gain Calibration Circuit……………………………... 8 3.2.2 Pulse Width Control Circuit…………………………. 11 3.2.3 Voltage-controlled Oscillator………………………… 13 3.2.4 Coarse Frequency Selector…………………………... 14 3.2.5 Divider……………………………………………….. 15 3.3 SSPLL Noise Analysis………………………………………. 16 3.4 Simulation Results…………………………………………... 17 3.5 Measurement Setup and Experiment Results……………….. 21 3.6 Performance Summary………………………………………. 31 4. Conclusion and Future Work………………………………………. 32 4.1 Conclusion……………………………………………………. 32 4.2 Future Work. …………………………………………………. 33 Bibliography ………………………………………………………………... 34 | |
| dc.language.iso | en | |
| dc.title | 一個使用迴路頻寬校正降低製程變異的2.4-3.0十億赫茲次取樣鎖相迴路 | zh_TW |
| dc.title | A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL with Loop Bandwidth Calibration | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 鄭國興(Kuo-Hsing Cheng),李泰成(Tai-Cheng Lee),林宗賢(Tsung-Hsien Lin) | |
| dc.subject.keyword | 頻寬校正,鎖相迴路,次取樣相位偵測器,脈衝寬度,迴轉率, | zh_TW |
| dc.subject.keyword | loop bandwidth calibration,phase-locked loop,sub-sampling phase detector,pulse width,slew rate, | en |
| dc.relation.page | 37 | |
| dc.identifier.doi | 10.6342/NTU202000832 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2020-05-18 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-109-1.pdf 目前未授權公開取用 | 4.8 MB | Adobe PDF |
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