基於電感性補償電壓合成變壓網路之Ka頻段功率放大器與D頻段功率放大器研究

Abstract

本論文探討毫米波與次太赫茲頻段高輸出功率 CMOS 放大器之設計，研究內容分為兩個部分，分別為 D 頻段之高輸出功率放大器設計，以及 Ka-band 變壓器式功率合成架構之理論分析與電路實現。 第一部分提出一個應用於 D 頻段之四路功率合成 CMOS 功率放大器，採用 65 奈米 CMOS 製程。針對次太赫茲頻段電晶體增益下降及被動元件損耗增加所造成之輸出功率限制，電路採用四路功率合成架構，並結合疊接組態（cascode）輸出級以提升輸出電壓擺幅。量測結果顯示，於 128 GHz 可達到 17.3 dBm 之飽和輸出功率，顯示所提出的架構可有效提升功率放大器之輸出功率。 第二部分探討 Ka-band 變壓器式功率合成架構。首先建立具補償電感的分佈式主動變壓器之集總等效電路模型，以分析耦合傳輸線與變壓器式功率合成架構之間的電路行為，提供較直觀之分析與設計方法。基於所建立之理論模型，分別設計四路 DAT 與串聯式變壓器兩種電壓合成 CMOS 功率放大器，以驗證所建立等效模型於不同變壓器式功率合成架構之適用性。量測結果顯示，兩個 Ka-band 功率放大器於 38 GHz 達到約 25.8 dBm 與26.2 dBm之飽和輸出功率，峰值功率附加效率分別為 24.4% 與 30.6%，顯示所提出之分析方法可作為高輸出功率毫米波 CMOS 功率放大器設計之參考。

This thesis investigates the design of high-output-power CMOS power amplifiers operating in the millimeter-wave and sub-terahertz frequency bands. The research consists of two parts: a high-output-power D-band power amplifier and the theoretical analysis and implementation of Ka-band transformer-based power-combining architectures. The first part presents a four-way power-combined CMOS power amplifier operating in the D-band and fabricated using a 65-nm CMOS process. To address the output power limitation caused by reduced transistor gain and increased passive losses at sub-terahertz frequencies, a four-way power-combining architecture together with a cascode output stage is adopted to increase the allowable output voltage swing. Measurement results show a saturated output power of 17.3 dBm at 128 GHz, demonstrating the capability of the proposed architecture to improve the output power of D-band CMOS power amplifiers. The second part investigates transformer-based power-combining architectures for Ka-band power amplifiers. First, a lumped equivalent-circuit model of an inductively compensated distributed active transformer (DAT) is established to analyze the circuit behavior of coupled transmission lines and transformer-based power-combining structures, providing a more intuitive approach for circuit analysis and design. Based on the proposed theoretical model, two four-way voltage-combining CMOS power amplifiers employing a distributed active transformer (DAT) and a series transformer (STF), respectively, are designed to verify the applicability of the proposed equivalent-circuit model to different transformer-based power-combining architectures. Measurement results show saturated output powers of 25.8 dBm and 26.2 dBm at 38 GHz, with peak power-added efficiencies of 24.4% and 30.6%, respectively. These results indicate that the proposed analysis method can serve as a useful reference for the design of high-output-power millimeter-wave CMOS power amplifiers.