邁向記憶體內運算之氧化物半導體電晶體電性調變技術

Abstract

隨著人工智慧運算需求持續增加，記憶體內運算（Computing-in-Memory, CIM）已成為突破傳統 Von Neumann 架構所造成之資料搬移瓶頸的重要技術。其中，以氧化物半導體電晶體（Oxide Semiconductor Field-Effect Transistor, OSFET）實現之 2T0C DRAM 因具備非破壞性讀取及良好的資料保持特性，而被視為具潛力之記憶體與類神經突觸元件。然而，OSFET 普遍存在臨界電壓（threshold voltage, VT）偏負的問題，因此如何有效調控其臨界電壓，已成為提升元件實用性的關鍵課題。 本論文採用閘極堆疊工程進行 OSFET 之臨界電壓調變，透過設計三種不同閘極堆疊結構（Baseline、WIZ 與 WISZ），成功實現約 ±30 mV 之雙向臨界電壓調變，同時維持相近之導通電流（on-current, ION）與次臨界擺幅，有望突破傳統臨界電壓調變方法中 VT–ION trade-off 的限制。接著，為進一步驗證其於記憶體及神經形態運算之應用潛力，本研究將上述 OSFET 元件應用於 2T0C DRAM 與類神經突觸元件。實驗結果顯示，採用較高臨界電壓之 OSFET 可有效降低關閉漏電流，進而減緩儲存節點電荷的流失，並提升 2T0C DRAM 之資料保持能力。此外，透過降低 2T0C 架構中讀取電晶體的閘極漏電流，可維持較高的儲存節點電壓，進而改善突觸元件之電導調變線性度與電導開關比，並提升神經網路之分類準確率。綜合上述結果，本研究不僅展示了 OSFET 之臨界電壓調變技術，更進一步提升了 OSFET 2T0C DRAM 之資料保持能力及神經網路準確率，顯示其於記憶體內運算及人工智慧硬體具有良好的應用潛力。

With the increasing demand for artificial intelligence (AI) computing, Computing-in-Memory (CIM) has emerged as a promising solution to overcome the data movement bottleneck of the conventional Von Neumann architecture. Among various memory technologies, oxide semiconductor field-effect transistor (OSFET)-based 2T0C DRAM has attracted considerable attention owing to its non-destructive read operation, excellent data retention, and potential for neuromorphic applications. However, the inherently negative threshold voltage (VT) of OSFETs limits their practical applications. In this work, gate stack engineering is employed to modulate the threshold voltage of OSFETs. Three gate stack structures, namely Baseline, WIZ, and WISZ, achieve bidirectional VT modulation of approximately ±30 mV while maintaining comparable on-current (ION) and subthreshold swing, showing the potential to overcome the conventional VT–ION trade-off. Furthermore, the proposed OSFETs are applied to 2T0C DRAM and synaptic devices. The results demonstrate that a higher-VT OSFET effectively suppresses leakage current and improves the data retention of the 2T0C DRAM. Moreover, reducing the gate leakage current of the read transistor improves synaptic performance, leading to higher neural network classification accuracy. Overall, this work demonstrates an effective VT engineering approach for OSFETs and the potential of OSFET-based 2T0C DRAM for CIM and AI hardware applications.