CVD生長的Bi2Se3堆疊雙層結構中的拓撲傳輸性質研究

Abstract

拓樸絕緣體（Topological Insulators, TIs）是一類具有絕緣體體相與金屬態表面態的量子材料，具有受到時間反轉對稱性(time reversal symmetry)保護的表面態，具備自旋與動量鎖定的性質，展現高度的抗反散射能力，為低功耗電子與自旋電子學元件提供潛力材料。其中，Bi2Se3 因其簡單的能帶結構（具有單一 Dirac Cone）、適中的體能隙(約 0.3 eV)與製程兼容性，成為研究 TIs 的代表性材料。 然而，實際元件中，體態導電、結構缺陷及會干擾表面態的傳輸特性，限制其應用潛力。本研究以化學氣相沉積法成長 Bi2Se3 薄膜，結合KOH蝕刻轉移技術製作垂直堆疊結構，藉此探討非外延式堆疊對 Bi2Se3 薄膜拓樸傳輸行為的影響。 本研究製備了單層、轉移單層與雙層堆疊之 Bi2Se3 樣品，並透過 X 光繞射（XRD）確認堆疊過程未破壞原有 R-3m 結構相。電阻隨溫度變化（R-T）結果顯示，單層樣品在低溫表現出表面主導傳輸的平臺行為，而雙層樣品則在 50 K 附近出現電阻極小值，並符合三維變範圍跳躍（3D Variable Range Hopping, VRH）模型，說明堆疊界面可能導致表面態混成與載子局域化。 磁阻（MR）量測進一步佐證雙層樣品的表面傳輸受限，僅在低場表現出微弱的弱反局域化（Weak Antilocalization, WAL）訊號，缺乏高場線性磁阻行為。此顯示非外延堆疊結構可能導致 Dirac 表面態的相干性破壞與拓樸保護削弱。 本研究揭示了非外延堆疊所引起的結構性擾動如何調控 Bi2Se3 拓樸表面態的傳輸機制，為未來利用層間工程實現可調控拓樸元件提供重要參考。

Topological insulators (TIs) represent a groundbreaking class of quantum materials characterized by an insulating interior and conductive surfaces. Their surface electronic states are safeguarded by time-reversal symmetry (TRS) and exhibit spin–momentum locking, which effectively suppresses backscattering. These attributes render TIs promising candidates for next-generation spintronic and energy-efficient electronic applications. Among them, Bi2Se3 has become a representative material for TI research due to its simple band structure with a Dirac cone, a moderate bulk bandgap (approximately 0.35 eV), and process compatibility. However, in actual devices, bulk conduction, structural defects, and non-ideal interfaces can interfere with the transport characteristics of the surface states, limiting its application potential. This study used chemical vapor deposition (CVD) to grow Bi2Se3 thin films, combined with KOH wet etching and transfer techniques to fabricate vertically stacked structures, in order to investigate how non-epitaxial stacking affects the topological transport behavior of Bi2Se3thin films. In this study, three types of Bi2Se3 sample were prepared: monolayer, transferred monolayer, and bilayer stacked. X-ray diffraction (XRD) analysis confirmed that the stacking process did not damage the original R–3m phase structure. Temperature-dependent resistance (R–T) results showed that the monolayer sample exhibited a resistance plateau at low temperatures, indicating surface-dominated transport. In contrast, the bilayer sample showed a resistance minimum around 50 K and followed the three-dimensional variable range hopping (3D VRH) model, indicating that stacking interfaces may lead to surface state hybridization and carrier localization. Magnetoresistance (MR) measurements further confirmed the suppression of surface transport in bilayer samples, showing only weak antilocalization (WAL) signals at low magnetic fields, and lacking the high-field linear MR behavior. This suggests that non-epitaxial stacking structures may destroy the coherence of Dirac surface states and weaken topological protection. This study reveals how structural perturbations introduced by non-epitaxial stacking can modulate the topological surface state transport mechanism in Bi2Se3, providing important reference value for achieving tunable topological devices through interlayer engineering.