應用於動態電壓與頻率調整之可程式化時脈產生器的機器學習預測方法

Abstract

可程式化時脈產生器廣泛應用於動態電壓與頻率調整系統中。在生產測試階段，必須於各供應電壓下找出最小時脈產生器控制碼。然而，傳統方法由最大控制碼開始向下搜尋，當起始控制碼與待測元件所需的最小控制碼相差較大時，將造成較長的測試時間。 本論文提出一種基於機器學習之自適應最小時脈產生器控制碼測試方法。本方法僅利用預測結果決定各晶片專屬的搜尋起始控制碼，最終的最小控制碼仍透過實際套用測試集進行確認，因此可在縮短測試時間的同時保證測試結果正確性。 為提升預測準確度，本方法使用環形振盪器、頻率範圍、晶粒位置、晶圓允收測試，以及先前較高供應電壓下已量測的最小控制碼作為輸入特徵。此外，於預測控制碼上加入保守邊界，以降低搜尋必須由最大控制碼重新開始的情況。 針對採用 3 奈米製程製造的 85,047 顆晶片進行實驗。結果顯示，相較於傳統測試流程，所提出的方法可將每顆晶片的測試程序執行次數降低 72.95%。

Programmable clock generators are widely used in dynamic voltage and frequency scaling systems. During production test, the minimum clock generator code must be identified at each supply voltage, but the conventional downward search from the maximum code can lead to long test time when the starting code is far above the minimum code required by the device under test. This thesis proposes a machine-learning-based adaptive minimum clock generator code test that uses prediction only to determine a chip-specific initial code, while the final minimum code is still identified through test set applications to guarantee correctness. Prediction accuracy is improved using ring oscillator, frequency range, die position, wafer acceptance test, and previously measured minimum codes from earlier supply voltages. A guardband is added to reduce restarts from the maximum code. Experimental results on 85,047 chips fabricated in a 3-nm process show that the proposed method achieves a 72.95% reduction in the number of test set applications compared with the conventional flow.