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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/103824| 標題: | 基於晶圓區域劃分之適應性測試最小工作電壓預測 Wafer-Zone-Based Vmin Prediction for Adaptive Test |
| 作者: | 王力揚 Li-Yang Wang |
| 指導教授: | 李建模 Chien-Mo Li |
| 關鍵字: | 晶片效能預測; 晶圓圖; 機器學習 Chip Performance Prediction; Wafermap; Machine Learning |
| 出版年 : | 2026 |
| 學位: | 碩士 |
| 摘要: | 本研究提出一套基於晶圓區域劃分之最小工作電壓預測架構,應用於適應性最小工作電壓測試。透過將晶圓層級的空間資訊納入機器學習預測模型中,本研究在提升預測準確度的同時,進一步降低生產測試時間。所提出之架構主要由晶圓區域分群、特徵工程與區域化建模三個部分組成。其中,晶圓區域分群利用空間相關性將晶圓劃分為多個區域,以捕捉局部製程變異特性。特徵工程則透過特徵生成與特徵篩選程序,建立具有代表性的輸入特徵,以提升模型預測能力。最後,針對各晶圓區域分別建立專屬預測模型,以學習不同區域中電性特徵與最小工作電壓之間的關係。
本研究以先進四奈米製程之二百一十萬顆晶粒進行實驗驗證。實驗結果顯示,相較於傳統線性迴歸方法,所提出之架構在單一自動測試設備電壓解析度判定條件下,預測準確度最高可提升4.03%。在兩倍自動測試設備電壓解析度判定條件下,各測試條件之預測準確度皆可達96%以上。此外,結合預測結果之適應性測試流程可在維持與傳統測試流程相同最小工作電壓量測準確度的前提下,將整體測試時間最多降低91.59%。研究結果顯示,將晶圓層級空間資訊導入最小工作電壓預測,可有效提升預測效能,並具備應用於適應性測試最佳化之潛力。 This work proposes a wafer-zone-based Vmin prediction framework for adaptive Vmin test. By incorporating wafer-level spatial information into machine-learning-based prediction, the proposed framework improves prediction accuracy while reducing production test time. The framework consists of three major components: wafer zone clustering, feature engineering, and zone-specific modeling. Wafer zone clustering partitions wafers into spatially correlated regions to capture localized process variation. Feature engineering generates informative features and applies feature selection to improve model effectiveness. Zone-specific regression models are then constructed to learn the localized relationships between measured features and Vmin. Experiments conducted on 2.1 million advanced 4nm dies demonstrate the effectiveness of the proposed approach. Compared with conventional linear regression, the proposed framework improves prediction accuracy by up to 4.03% under the one-ATE-resolution criterion. Under the two-ATE-resolution criterion, prediction accuracy exceeds 96% across all test conditions. Furthermore, the adaptive test flow reduces overall test time by up to 91.59% while guaranteeing the same Vmin accuracy as the conventional testing flow. The results demonstrate that incorporating wafer-level spatial information is an effective approach for accurate Vmin prediction and adaptive test optimization. |
| URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/103824 |
| DOI: | 10.6342/NTU202601471 |
| 全文授權: | 同意授權(全球公開) |
| 電子全文公開日期: | 2026-08-20 |
| 顯示於系所單位: | 電子工程學研究所 |
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| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-114-2.pdf | 3.99 MB | Adobe PDF | 檢視/開啟 |
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