基於大型語言模型之可靠且具資料效率的 Verilog 程式碼生成與測試平台自動化

Abstract

近年來，隨著大型語言模型(LLMs)的崛起，利用語言模型產生程式碼已成為研究的主流之一。然而，相較於軟體程式語言，現有的模型在硬體描述語言(HDLs)的表現上仍受限許多。其瓶頸主要歸咎於訓練資料的稀缺性，以及品質的參差不齊。為了解決此問題，本研究提出一個專門用於產生高品質Verilog模型訓練資料與測試平台(Testbench)的自動化多代理系統(Multi-Agent)架構。我們的核心貢獻包含兩點：一、將訓練資料的生成任務拆解為多個階段，並交由各自的Agent處理，提升產出資料的可靠性。二、提出預處理機制(Pre-generation Mechanism)，針對結構完整、品質較佳的候選資料進行流程縮減，在提升計算效率的同時，進一步提升資料生成的整體成功率。研究結果顯示，在VerilogEval-v2-NTU的基準測試上，本研究提出的架構能在只使用同類研究約一半的訓練資料下，達到與最先進的模型相近的成績。

In recent years, with the rise of Large Language Models (LLMs), code generation using language models has become a dominant research topic. However, compared to software programming languages, existing models are still significantly limited in their performance with Hardware Description Languages (HDLs). This critical bottleneck is mainly due to the scarcity of training data and its inconsistent quality. To address these challenges, this study proposes an automated multi-agent framework designed for the high-quality generation of Verilog training data and associated testbenches. The core contributions of this research are twofold: 1) We break down the task of generating training data into multiple stages and assign each stage to a separate agent, improving the reliability of the generated data. 2) We introduce a pre-generation mechanism that streamlines the processing pipeline for structurally sound, high-quality candidate data. This improves computational efficiency while also increasing the overall data generation success rate. Experimental results demonstrate that on the VerilogEval-v2-NTU benchmark, the proposed architecture achieves performance comparable to that of state-of-the-art models while using only about half the amount of training data used in concurrent peer studies.