具有自舉式電路的三階降壓轉換器並實現啟動飛電容平衡

Abstract

在前人的研究中[1]，所提出之完整閉迴路三階降壓轉換器架構因功率級（Power Stage）無法正常切換，面臨了操作瓶頸。為深入分析並突破此硬體限制，本論文提出一款整合自舉（Bootstrap）電路與上電飛電容平衡機制之三階降壓轉換器積體電路。所提出架構透過自舉電路提供高側功率開關所需之閘極驅動電壓，並結合上電飛電容平衡機制，使系統於啟動階段建立穩定操作條件。本研究採用全 NMOS 功率電晶體架構，分別基於 TSMC 0.18-μm CMOS Mixed Signal RF General Purpose Standard Process（T18）與 CMOS High Voltage Mixed Signal Based Generation II Process（T18HVG2），完成共五個晶片版本之設計與實作。透過多代晶片之實驗量測與交叉分析，本研究逐步驗證並改善具潛在操作限制之子電路模組。實驗結果顯示，晶片內部死區時間控制電路可正常運作並具備良好調整彈性；同時，自舉電容與飛電容（Flying Capacitor）於預充電階段皆可成功建立至預期電位。經由系統化除錯與架構改善後，本研究最終於 T18HVG2 製程晶片中成功驗證單晶片三階降壓轉換器之穩態操作能力。在2 MHz外部 PWM 訊號驅動下，關鍵功率切換節點皆呈現正常動態切換行為。於輸入電壓 2.5V、占空比 10% 之無載條件下，輸出電壓 VOUT可穩定維持於 0.25V，且電感電流成功運作於強制連續導通模式（Forced Continuous Conduction Mode, FCCM）；當輸入電壓提升至 3.3V、占空比 25% 時，電路仍可維持正常操作並完成預期降壓轉換。本研究不僅針對前人功率級操作瓶頸進行分析與驗證，更透過 T18HVG2 製程實測結果證實全整合單晶片三階降壓轉換器架構之可行性，並為後續整合閉迴路控制以實現完整單晶片 PMIC 奠定工程基礎。

In the prior work [1], the proposed fully closed-loop three-level (3-level) buck converter architecture encountered operational bottlenecks due to the inability of the power stage to switch properly. To investigate and improve these hardware limitations, this thesis proposes a fully integrated 3-level buck converter IC incorporating bootstrap circuits and a pre-charge flying capacitor balancing mechanism. The proposed architecture utilizes bootstrap circuits to provide the required gate-driving voltage for high-side power switches and integrates a pre-charge flying capacitor balancing mechanism to establish stable operating conditions during the start-up period.

An all-NMOS power transistor configuration was adopted, and five chip generations were designed and fabricated based on two TSMC 0.18-μm processes: the CMOS Mixed Signal RF General Purpose Standard Process (T18) and the CMOS High Voltage Mixed Signal Based Generation II Process (T18HVG2). Through experimental measurements and cross-comparison among multiple chip generations, sub-circuit blocks with potential operational limits were systematically analyzed and improved.

Experimental results demonstrate that the on-chip dead-time control circuit operates correctly with good adjustment flexibility. Meanwhile, both the bootstrap capacitor and flying capacitor successfully achieve their expected voltage levels during the pre-charging phase. After systematic debugging and architectural improvements, the proposed fully integrated 3-level Buck converter successfully achieves steady-state operation verification in the T18HVG2 process implementation. Under an external PWM driving frequency of 2 MHz, all critical power switching nodes exhibit correct dynamic switching behaviors. With an input voltage of 2.5V and a duty cycle of 10% under a no-load condition, the output voltage VOUT is successfully maintained at 0.25 V, and the inductor current operates in Forced Continuous Conduction Mode (FCCM). Furthermore, when the input voltage is increased to 3.3 V with a duty cycle of 25%, the converter maintains stable switching operation and achieves the expected step-down voltage conversion.

This research not only analyzes and validates the hardware limitations responsible for the previous power-stage operational bottlenecks but also experimentally demonstrates the feasibility of the proposed fully integrated on-chip 3-level Buck converter architecture through the successful T18HVG2 implementation. The presented results establish a solid engineering foundation for future integration of closed-loop control toward a complete monolithic PMIC.