基於AI代理之設計準備與網路晶片架構探索框架之研究

Abstract

隨著晶片設計規模與複雜度呈指數級成長，系統級晶片（SoC）面臨極高的設計成本與開發時程壓力。若無法在系統架構設計階段（System-level）精準鎖定最佳架構，直接進入後端實體設計往往導致高昂的重工風險。此外，現行架構探索流程中，規格描述與輸入配置極度繁瑣耗時；且隨著核心數量的增加，傳統點對點（Point-to-point）或匯流排（Bus）連接方案已無法滿足頻寬與延遲需求，轉而必須依賴具高度擴展性之晶片網路（NoC）架構。然而，如何自動化配置多樣化的 NoC 並快速評估其效能，成為當前架構探索之核心挑戰。

為了解決上述挑戰，本論文提出一套基於 AI 代理之自動化晶片網路架構探索框架。此系統允許使用者透過高階自然語言定義晶片規格，藉由 AI Agent 引導使用者完成設計準備（Design Preparation）工作，並能自動產生並評估多種 NoC 拓撲組合。為降低週期精確模擬的成本，本研究提出兩類互補的加速策略：第七章的 offered-load sweep sampling 可減少完成 Pareto 篩選所需的 BookSim 執行次數，第八章的 BookSim 模擬器優化則縮短單次模擬時間；並結合基於帕雷托（Pareto）原則的拓撲篩選，在龐大搜尋空間中更有效率地找出效能轉折點（Knee point）。

為了驗證本框架之有效性，本研究導入四大產業架構啟發之 SoC 基準測試（industry-inspired SoC benchmarks），涵蓋多家半導體巨頭之真實晶片架構規模與通訊特徵，以進行全面的架構探索與效能評估。實驗結果顯示，本系統不僅能有效收斂至 Pareto 最優架構候選集，更透過自動化流程顯著提升了探索搜尋的效率，減少了架構師在規格定義與模擬配置上的負擔。此研究成功實現了架構設計左移（Shift-Left）之目標，提供一套自動、高效且具備決策輔助能力的系統，有效解決了 SoC 設計初期面臨的架構選擇難題，對於提升次世代晶片設計之研發效率與決策品質具有關鍵參考價值。

As the scale and complexity of chip design grow exponentially, System-on-Chip (SoC) development faces escalating costs and tight time-to-market pressures. Failure to pinpoint an optimal architecture during the early system-level design phase often necessitates costly design iterations in the back-end physical implementation. Furthermore, the current architectural exploration workflow is hampered by tedious and time-consuming specification definition and configuration. As core counts continue to rise, traditional point-to-point or bus-based interconnects can no longer satisfy bandwidth and latency requirements, shifting the design paradigm toward scalable Network-on-Chip (NoC) architectures. Nevertheless, automating the configuration of diverse NoC topologies and efficiently evaluating their performance remains a core challenge in architectural exploration.

To address these challenges, this thesis proposes an AI agent-based automated NoC architecture exploration framework. This system enables users to define chip specifications through high-level natural language; an AI agent then guides them through design preparation interactively and the framework automatically generates and evaluates multiple NoC topologies. To reduce the cost of cycle-accurate evaluation, we employ two complementary acceleration strategies: selective offered-load sweep sampling (Chapter~7), which reduces the number of BookSim runs needed for knee-point and Pareto analysis, and BookSim simulator optimizations (Chapter~8), which shorten per-run simulation time. These techniques are combined with a Pareto-based topology selection strategy to navigate the exploration search space more efficiently.

To validate the effectiveness of this framework, we introduced four industry-inspired SoC benchmarks, covering the architectural scales and communication characteristics of state-of-the-art designs from major semiconductor industry leaders. Experimental results demonstrate that our system not only effectively converges on a Pareto-optimal set of architectural candidates but also significantly enhances exploration efficiency by streamlining the automation workflow and reducing the manual burden of specification definition and simulation configuration. This research successfully achieves the goal of "shifting left" in the architectural design cycle, providing an automated, efficient, and decision-supportive system that effectively resolves the challenges of early-stage SoC architectural selection, offering significant value for improving the research efficiency and decision-making quality of next-generation chip design.