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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 胡振國 | zh_TW |
| dc.contributor.advisor | Jenn-Gwo Hwu | en |
| dc.contributor.author | 汪佳穎 | zh_TW |
| dc.contributor.author | Chia-Ying Wang | en |
| dc.date.accessioned | 2026-07-22T17:04:56Z | - |
| dc.date.available | 2026-07-23 | - |
| dc.date.copyright | 2026-07-22 | - |
| dc.date.issued | 2026 | - |
| dc.date.submitted | 2026-07-06 | - |
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Hwu, "Role of Schottky Barrier Height Modulation on the Reverse Bias Current Behavior of MIS(p) Tunnel Diodes," (in English), IEEE ACCESS, vol. 9, pp. 163929–163937, 2021, doi: 10.1109/ACCESS.2021.3133575. [12] Y.-C. Tsai and J.-G. Hwu, "Prolonged Transient Current Behavior and Memory Application of Coupling Concentric Metal-Insulator-Semiconductor Tunnel Diodes (MISTDs)," in Electrochemical Society Meeting Abstracts 247, 2025, no. 36: The Electrochemical Society, Inc., pp. 1730–1730. [13] S.-W. Huang and J.-G. Hwu, "Study and optimization of two-state transient currents at millisecond time scales in MIS tunnel diodes," IEEE Transactions on Electron Devices, vol. 70, no. 10, pp. 4999–5006, 2023. [14] C.-Y. Kao, S.-W. Huang, and J.-G. Hwu, "Study on the transient behaviors of concentric MIS tunneling diodes by rapid voltage switching at ring/center and read at center/ring," IEEE Transactions on Electron Devices, vol. 72, no. 1, pp. 364–369, 2024. [15] H.-T. Lue, T.-H. Hsu, Y.-H. Hsiao, S.-C. Lai, E.-K. Lai, S.-P. Hong, M.-T. Wu, F. Hsu, N. Lien, and C.-P. Lu, "Understanding STI edge fringing field effect on the scaling of charge-trapping (CT) NAND Flash and modeling of incremental step pulse programming (ISPP)," in 2009 IEEE International Electron Devices Meeting (IEDM), 2009: IEEE, pp. 1–4. [16] K. Choi, F. Yesilkoy, G. Ryu, S. H. Cho, N. Goldsman, M. Dagenais, and M. Peckerar, "A focused asymmetric metal–insulator–metal tunneling diode: fabrication, DC characteristics and RF rectification analysis," IEEE Transactions on Electron Devices, vol. 58, no. 10, pp. 3519–3528, 2011. [17] J. Kim, S. M. Wi, J. G. Ahn, S. Son, H. Lim, Y. Park, H. J. Eun, J. B. Park, H. Lim, and S. Pak, "Engineering geometric electrodes for electric field‐enhanced high‐performance flexible in‐plane micro‐supercapacitors," Energy & Environmental Materials, vol. 6, no. 4, p. e12581, 2023. [18] K.-C. Chen, K.-W. Lin, S.-W. Huang, J.-Y. Lin, and J.-G. Hwu, "Comprehensive study of inversion capacitance in metal-insulator-semiconductor capacitor with existing oxide charges," IEEE Journal of the Electron Devices Society, vol. 10, pp. 960–969, 2022. [19] S.-W. Huang and J.-G. Hwu, "Transient current enhancement in MIS tunnel diodes with lateral electric field induced by designed high-low oxide layers," IEEE Transactions on Electron Devices, vol. 68, no. 12, pp. 6580–6585, 2021. [20] C. S. Liao, W. C. Kao, and J. G. Hwu, "Energy-Saving Write/Read Operation of Memory Cell by Using Separated Storage Device and Remote Reading With an MIS Tunnel Diode Sensor," (in English), IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, vol. 4, no. 6, pp. 424–429, NOV 2016, doi: 10.1109/JEDS.2016.2591956. [21] Jian-Yu Lin, "Enhance Transient current ment Eehavior in MIS(p) Tunneling Diodes with Gate Edge Trench Structure," Master’s Thesis, National Taiwan University, 2021. [22] Y.-K. Lin, L. Lin, and J.-G. Hwu, "Minority carriers induced Schottky barrier height modulation in current behavior of metal-oxide-semiconductor tunneling diode," ECS Journal of Solid State Science and Technology, vol. 3, no. 6, pp. Q132–Q135, 2014. [23] R.-X. Wang, "Enhanced Transient Current Behavior and Its Memory Application in Concentric Gate Metal-Insulator-Semiconductor Tunnel Diodes with Center Oxide Local Thinning," Master’s Thesis, National Taiwan University, 2024. [24] Y.-K. Lin and J.-G. Hwu, "Role of Lateral Diffusion Current in Perimeter-Dependent Current of MOS(p) Tunneling Temperature Sensors," IEEE TRANSACTIONS ON ELECTRON DEVICES, Article vol. 61, no. 10, pp. 3562–3565, 2014 OCT 2014, doi: 10.1109/TED.2014.2346238. [25] C.-C. Lin, P.-L. Hsu, L. Lin, and J.-G. Hwu, "Investigation on edge fringing effect and oxide thickness dependence of inversion current in metal-oxide-semiconductor tunneling diodes with comb-shaped electrodes," Journal of Applied Physics, vol. 115, no. 12, 2014. [26] H.-W. Lu and J.-G. Hwu, "Lateral nonuniformity of the tunneling current of Al/SiO2/p-Si capacitor in inversion region due to edge fringing field effect," Electrochemical Society Transactions 224, vol. 58, no. 7, pp. 339–344, 2013. [27] H.-H. Lin and J.-G. Hwu, "Influence of Etching-Induced Surface Damage on Device Performance With Consideration of Minority Carriers Within Diffusion Length From Depletion Edge," IEEE TRANSACTIONS ON ELECTRON DEVICES, Article vol. 62, no. 2, pp. 634–640, 2015 FEB 2015, doi: 10.1109/TED.2014.2382651. [28] Pi-Hung Chen, "Study of the Hydrogen Effect on Si-SiO2 Interface Property for MOS Capacitor after Water Immersion," Master’s Thesis, National Taiwan University, 2006. [29] C. Y. Kao, S. W. Huang, H. X. Shih, W. C. Lin, S. Y. Feng, and J. G. Hwu, "Role of oxide charges on the voltage and current coupling effects between adjacent devices examined by concentric metal-insulator-semiconductor (MIS) tunnel diodes with ultra-thin oxide," (in English), PHYSICA SCRIPTA, vol. 99, no. 10, OCT 1 2024, Art no. 105578, doi: 10.1088/1402-4896/ad7cd6. [30] W. Guo, S. K. Anantharajan, K. Liu, and H. Deng, "Investigation of electrochemical oxidation behaviors and mechanism of single-crystal silicon (100) wafer under potentiostatic mode," Coatings, vol. 10, no. 6, p. 586, 2020. [31] A. Revesz, "The role of hydrogen in SiO2 films on silicon," Journal of the Electrochemical Society, vol. 126, no. 1, pp. 122–130, 1979. [32] Y.-C. Tsai, "Current Polarity Reversal Behavior in Concentric Metal-Insulator-Semiconductor Tunnel Diodes with High-Low Oxide Structure and Its Application on Logic Operations and Transient Memory," Master’s Thesis, National Taiwan University, 2025. [33] E. Nicollian and A. Goetzberger, "The si-sio, interface–electrical properties as determined by the metal-insulator-silicon conductance technique," The Bell System Technical Journal, vol. 46, no. 6, pp. 1055–1033, 1967. [34] D. Klaassen, "A unified mobility model for device simulation," in International Technical Digest on Electron Devices, 1990: IEEE, pp. 357–360. [35] W. Shockley and W. Read Jr, "Statistics of the recombinations of holes and electrons," Physical review, vol. 87, no. 5, p. 835, 1952. [36] G. Iannaccone, G. Curatola, and G. Fiori, "Effective Bohm Quantum Potential for device simulators based on drift-diffusion and energy transport," in Simulation of Semiconductor Processes and Devices 2004: Springer, 2004, pp. 275–278. [37] W.-C. Lee and C. Hu, "Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction-and valence-band electron and hole tunneling," IEEE Transactions on Electron Devices, vol. 48, no. 7, pp. 1366–1373, 2001. [38] T. Collins and J. Churchill, "Exact modeling of the transient response of an MOS capacitor," IEEE Transactions on Electron Devices, vol. 22, no. 3, pp. 90–101, 2005. [39] S.-Y. Oh, D. E. Ward, and R. W. Dutton, "Transient analysis of MOS transistors," IEEE Journal of Solid-State Circuits, vol. 15, no. 4, pp. 636–643, 1980. [40] H. Sung-Wei, "Transient Current Behavior in MIS Tunnel Diodes," Doctoral Dissertation, National Taiwan University, 2024. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/102866 | - |
| dc.description.abstract | 本論文旨在探討結合齒輪狀閘極結構（Gear-shaped gate architecture）與非平面厚薄氧化層（High-Low oxide）結構之金氧半穿隧二極體（MISTD）的電性與橫向耦合效應，並深入分析其在暫態記憶體（Transient memory）上的應用潛力。有別於傳統平面結構元件在極端微縮時電流的記憶視窗降低的瓶頸，本研究提出的創新閘極結構，能有效在縮減元件面積的同時，大幅強化暫態電流的記憶視窗。
在第一章中，我們首先回顧了金氧半穿隧二極體的基本電性，以及用於生長氧化層的陽極氧化製程與 Silvaco TCAD模擬軟體的參數設定。第二章探討了平面 MISTD 在暫態記憶體在微縮時的物理限制，並引入創新設計之「耦合齒輪狀閘極結構」。從實驗結果與TCAD模擬皆證實，此結構能藉由高曲率的邊緣強化局部邊緣電場並提升周長面積比，在面積大幅微縮的情況下增強橫向耦合，藉此提升暫態記憶體的效能。而第三章進一步將厚薄氧化層（High-Low oxide）結構整合至元件中，探討其等效微縮之行為。透過在特定區域配置厚氧化層以阻擋非必要的垂直穿隧漏電流，並在邊緣保留薄氧化層以維持關鍵的橫向耦合路徑，此設計成功模擬了元件在微縮下的優異表現。最後，第四章總結本論文之主要研究成果，並針對未來在記憶體技術的發展提出改進建議與展望。 | zh_TW |
| dc.description.abstract | This thesis investigates the electrical characteristics and lateral electrostatic coupling effects of metal-insulator-semiconductor tunnel diodes (MISTDs) featuring a novel coupling gear-shaped gate architecture and a non-planar high-low (HL) oxide structure, comprehensively evaluating their potential for transient memory applications. Addressing the critical bottleneck of memory window degradation in conventional planar devices under aggressive physical scaling, the proposed structural and dielectric innovations effectively minimize the device footprint while substantially amplifying the transient memory window.
The thesis is organized as follows. Chapter 1 reviews the fundamental device physics of MISTDs, the anodic oxidation fabrication process, and the parameter configurations for Silvaco TCAD numerical simulations. Chapter 2 explores the physical scaling limitations of planar MISTDs and introduces the coupling gear-shaped gate architecture. Both experimental characterizations and TCAD simulations demonstrate that the high-curvature gear edges intensify localized fringing electric fields and maximize the effective perimeter-to-area ratio. This structural engineering significantly enhances lateral carrier coupling and memory performance despite a drastically reduced device area. Chapter 3 integrates the non-planar HL oxide structure to investigate the "equivalent scaling" behavior of the device. By strategically deploying a thick oxide region to suppress unnecessary vertical tunneling leakage while preserving a thin oxide at the electrode periphery to maintain the critical lateral coupling path, this approach successfully emulates and validates the robust device performance under extreme scaling conditions. Finally, Chapter 4 summarizes the core experimental findings and provides prospects for the future development of capacitor-less memory technologies. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2026-07-22T17:04:56Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2026-07-22T17:04:56Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員會審定書 I
誌謝 II 摘要 III Abstract IV Contents VI Table Captions VIII Figure Captions IX Chapter 1 Introduction 1 1-1 Motivation and Thesis Organization 2 1-2 Electrical Characteristics of MIS(p) Tunnel Diodes 4 1-2-1 Influence of Oxide Thickness in MISTDs 4 1-2-2 Perimeter Influence on Reverse Bias Current 5 1-2-3 Non-Uniformity Effect in MISTDs with Ultrathin Oxides 6 1-2-4 Transient Behaviors in MISTDs 7 1-3 Oxide Growth Mechanism by Anodic Oxidation 8 1-4 TCAD Simulation Setup and Configuration 9 1-5 Summary 10 Chapter 2 Effect of Coupling Gear-Shaped Gate Architecture on Transient Current of Planar MIS Tunnel Diodes 13 2-1 Introduction 14 2-2 Experimental 15 2-3 Results and Discussion 16 2-3-1 Electrical Characteristics of Planar MISTDs for Transient Memory Applications 16 2-3-2 Improvement of Transient Behavior in Planar MISTDs by Designed Coupling Gear-Shaped Gate Architecture 18 2-3-3 Comparison of Coupling Effects in Gear-Shaped Gates with Different Gear Numbers 21 2-3-4 TCAD Simulation Results 23 2-4 Summary 25 Chapter 3 Influence of High-Low Oxide Structure on Transient Memory Characteristics 41 3-1 Introduction 42 3-2 Experimental 43 3-3 Results and Discussion 44 3-3-1 Equivalent Scaling Behavior through High-Low Oxide Structure 44 3-3-2 Influence of Modulating High-Low Oxide Structure Ratio on Transient Current 45 3-3-3 Carrier Analysis Inside High-Low Oxide Structure 47 3-3-4 TCAD Simulation Results 50 3-4 Summary 51 Chapter 4 Conclusion and Future Work 66 4-1 Conclusion 67 4-2 Suggestion for Future Work 69 Reference 72 | - |
| dc.language.iso | en | - |
| dc.subject | 金氧半穿隧二極體 | - |
| dc.subject | 耦合效應 | - |
| dc.subject | 暫態電流特性 | - |
| dc.subject | 低功耗 | - |
| dc.subject | 厚薄氧化層 | - |
| dc.subject | 高面積效率佈局 | - |
| dc.subject | 新型閘極結構 | - |
| dc.subject | 多位元 | - |
| dc.subject | 動態記憶體 | - |
| dc.subject | Metal-Insulator-Semiconductor Tunnel Diode (MISTD) | - |
| dc.subject | Coupling Effect | - |
| dc.subject | Transient Current Characteristics | - |
| dc.subject | Low-Power Consumption | - |
| dc.subject | High-Low oxide | - |
| dc.subject | Area-Efficient Layout | - |
| dc.subject | Novel Gate Structure | - |
| dc.subject | Multi-Level Cell (MLC) | - |
| dc.subject | Dynamic Memory | - |
| dc.title | 具耦合齒輪狀閘極與厚薄氧化層結構之金氧半穿隧二極體暫態記憶體 | zh_TW |
| dc.title | MIS Tunnel Diode Transient Memory Based on a Coupling Gear-Shaped Gate Architecture and High-Low Oxide Structure | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 114-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.coadvisor | 吳肇欣 | zh_TW |
| dc.contributor.coadvisor | Chao-Hsin Wu | en |
| dc.contributor.oralexamcommittee | 林浩雄;吳幼麟 | zh_TW |
| dc.contributor.oralexamcommittee | Hao-Hsiung Lin;You-Lin Wu | en |
| dc.subject.keyword | 金氧半穿隧二極體; 耦合效應; 暫態電流特性; 低功耗; 厚薄氧化層; 高面積效率佈局; 新型閘極結構; 多位元; 動態記憶體 | zh_TW |
| dc.subject.keyword | Metal-Insulator-Semiconductor Tunnel Diode (MISTD); Coupling Effect; Transient Current Characteristics; Low-Power Consumption; High-Low oxide; Area-Efficient Layout; Novel Gate Structure; Multi-Level Cell (MLC); Dynamic Memory | en |
| dc.relation.page | 77 | - |
| dc.identifier.doi | 10.6342/NTU202601379 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2026-07-06 | - |
| dc.contributor.author-college | 重點科技研究學院 | - |
| dc.contributor.author-dept | 元件材料與異質整合學位學程 | - |
| dc.date.embargo-lift | N/A | - |
| 顯示於系所單位： | 元件材料與異質整合學位學程 | |
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