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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電機工程學系
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/10280
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor陳怡然
dc.contributor.authorWen-Tung Yangen
dc.contributor.author楊文棟zh_TW
dc.date.accessioned2021-05-20T21:16:37Z-
dc.date.available2011-02-09
dc.date.available2021-05-20T21:16:37Z-
dc.date.copyright2011-02-09
dc.date.issued2011
dc.date.submitted2011-01-26
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[6] Jorge Varona, Anas A. Hamoui, and Ken Martin, 'A low-voltage fully-monolithic
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[7] Eric Gaalaas, Bill Yang Liu, Naoaki Nishimura, 'Integrated stereo delta-sigma
class d amplifier,' in ISSCC Dig. Tech. Papers, pp. 120-121, Dec. 2005.
[8] Kyoungsik Kang, Jeongjin Roh, Youngkil Choi, Hyungdong Roh, Hyunsuk Nam,
and Songjun Lee, 'Class-d audio amplifier using 1-bit fourth-order delta-sigma
modulation,' IEEE Tran. on Circuits Syst. II, Exp. Briefs, vol. 50, no. 11,
pp. 728-732, Aug. 2008.
[9] Lukas Dorrer, Franz Kuttner, Patrizia Greco, Patrick Torta, and Thomas Hartig, 'A
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no. 12, pp. 2416-2427, Dec. 2005.
[10] Yasuyuki Matusuya, Kuniharu Uchimura, Atsushi Iwata, and Tsutomu Kobayashi,
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Dec. 1987.
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conversion,' IET J. Electronic and Communication Engineering, vol. 10, issue1,
pp.37-47, 1998.
[16] Ian Galton, and Henrik T. Hensen, 'Oversampling parallel delta-sigma modulator
a/d conversion,' IEEE Tran. on Circuits Syst. II, Analog Digit. Signal Process.,
vol. 43, no. 12, Dec. 1996.
[17] C. Budsabathon and A. Nishihara, 'Design of high order stable delta sigma
modulator with state space approach,' in IEEE Tecon, vol. A, Nov. 2004.
pp.523-526
[18] W.L. Lee, 'A novel interpolative modulator topology for high resolution
oversampling a/d converters,' Master’s Thesis, Massachusetts Institute of
Technology, Cambridge, MA, June 1987.
[19] G. Troster, P. Ferguson, K. Schoppe, A. Wedel, E. Zocher, J. Arndt, H-J. Dressler,
H-J Golberg and W. Schardein, 'An interpolative bandpass converter on a 1.2mm
bi-cmos analog/digital array,' IEEE J. of Solid-State Circuits, vol. 28,
no.4, pp.471-477, Apr. 1993.
[20] G. I Bourdopouos, A. Pnevmatikakis, V. Anastassopouos and T. L Deliyannis,
Delta-Sigma Modulators: Modeling, Design and Application. Imperial College
Press, 2006.
[21] W. Chou, P. Wong, R. Gray, 'Multi-stage sigma-delta modulation,' IEEE Trans.
Information Theory, vol. 35, pp. 784-796, July 1989.
[22] Eric J. Van der Zwan and E. Carel Dijkmans, 'A 0.2mW cmos delta sigma
modulator for speech coding with 80dB dynamic range,' IEEE J. of Solid-State
Circuits, Vol.31, No. 12, pp.1873-1880, Dec. 1996.
[23] Richard scherier, and Gabor C. Themes, Understanding Delta Sigma Data
Converters. , Wiley, IEEE Press, 2004.
[24] 劉深淵, 楊清淵, 鎖相迴路 , in Chapter 3, 滄海書局, Nov. 2006.
[25] N. Christoffers, R. Kokozinski, S. Kolnsberg, and B.J. Hosticka, 'High
loop-filter-order ΣΔ-fractional-n frequency synthesizers for use in
frequency-hopping spread-spectrum communication-systems,' in Proc. IEEE
ISCAS, May, 2003, pp.216-219.
[26] Tom A. D. Riley, Miles A. Copeland, 'Delta-sigma modulation in fractional-n
frequency synthesis,' IEEE J. of Solid-State Circuits, vol. 28, No. 5,
pp.553-559, May 1993.
[27] Terrence p. Kenny, Thomas A.D. Riley, Norman M. Filiol, and Miles A. Copeland.
'Design and realization of a digital ΔΣ modulator for fractional-n frequency
synthesis,' IEEE Trans. Vehicular Technology, vol. 48, No. 2, pp. 510-521,
March 2009.
[28] Chun-Pang Wu, Hen-Wai Tsao, and Jingshown Wu, 'A novel sigma-delta
fractional-n synthesizer architecture with fractional spur and quantization noise
cancellation,' in Proc. IEEE ISCAS, May 2010, pp. 1117-1120.
[29] Eric Gaalaas, Bill Yang Liu, Naoaki Nishimura, Robert Adams, and
Karl Sweetland, 'Integrated stereo ΔΣ class d amplifier,' IEEE J. of Solid-State
Circuits, vol. 40, No. 12, pp.2388-2396, Dec. 2005.
[30] Jun Honda, and Jonathan Adams, 'Class d audio amplifier basics,' Application
Note AN-1071, International Rectifier.
[31] Joseph S. Chang, Meng-Tong Tan, Zhihong Cheng, and Yit-Chow Tong, 'Analysis
and design of power efficient class d amplifier output stages,' IEEE Trans. Circuits
Syst., vol. 47, no. 6, pp.897-902, June 2000.
[32] Kirk C. H. Chao, Shujaat Nadeem, Wai L. Lee, and Charles G. Sodini, 'A higher
order topology for interpolative modulators for oversampling a/d converters,'
IEEE Trans. Circuits Syst, vol. 37, no. 3, pp.196-205, March 1990.
[33] http://www.mathworks.com/matlabcentral/fileexchange/19
[34] Behzad Razavi, Design of Analog CMOS Integrated Circuits. MaGraw-Hill,
2002.
[35] Richard Schreier, and Trevor Caldwell, Advanced Analog Circuits Notes.
[36] http://www.national.com/mpf/LM/LM4665.html#Overview
[37] http://www.national.com/mpf/LM/LM4666.html#Overview
[38] http://www.national.com/mpf/LM/LM4667.html#Overview
[39] http://www.national.com/mpf/LM/LM4670.html#Overview
[40] C. W. Lin, Y. P. Lee, and W. T. Chen, 'A 1.5 bit 5th order ct/dt delta sigma class d
amplifier with power efficiency improvement,' in Proc. IEEE ISCAS, May 2008,
pp. 280-283.
[41] A. Matamura, N. Nishinmura, and B. Y. Liu, 'Filterless multi-level delta-sigma
class-d amplifier for portable applications,' in Proc. IEEE ISCAS, May 2009, pp.
1177-1180.
[42] Yang Boon Quek, 'Application report, SLOA119A- April,'
http://focus.tij.co.jp/jp/lit/an/sloa119a/sloa119a.pdf, T.I. INC. 2006.
[43] J. S. Chang, B. H. Gwee, Y. S. Lon, and M. T. Tan, 'A novel low-power
low-voltage class d amplifier with feedback for improving thd power effiency and
gain linearity,' in Proc. IEEE ISCAS, May 2001, pp. 635-638.
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/10280-
dc.description.abstract本論文討論了三角積分調變器的數位及類比兩種應用,前者可應用在數位類比轉換器以及非整數除頻器上;後者可應用在類比數位轉換器、直流-直流電壓轉換器及切換式功率放大器上。最後依據數位及類比的應用,設計了應用在非整數除頻器以及非線性切換式功率放大器之兩種三角積分調變器。
藉由應用非整數除頻器在非整數頻率合成器上,可以減少鎖定時間及縮短通道頻率間距。本論文設計一個採用預先進位加法器實現的數位MASH 1-1-1架構,可配合多除數除頻器達到非整數除頻的效果。
非線性放大器已經被大量應用在手持式行動裝置的音頻放大器上,最明顯的好處在於功率效能高,能提升電池使用時間,降低熱損耗。然而相較於線性放大器來說,總諧波失真較高,因此只能應用在對音質要求較低的音頻系統。本論文設計一個三階的類比三角積分調變器,完成音頻D類放大器整體系統模擬。
zh_TW
dc.description.abstractApplications of the delta-sigma modulator in digital and analog circuits are discussed in this thesis. Delta sigma modulator can be used in digital circuits such as digital-to-analog converters and fraction-N frequency synthesizers; or in analog circuits such as analog-to-digital converters, DC-DC converters and switched-mode power amplifiers. According to these applications, a digital modulator for fractional divider and an analog modulator for nonlinear switched-mode power amplifier are proposed in the thesis.
We can decrease locking time and reduce channel bandwidth by applying fractional divider in fractional-N frequency synthesizers. Therefore, a digital MASH 1-1-1 modulator based on the carry-look-ahead adder which can integrate with multi-modulus divider to realize the fractional division function is designed and presented in this thesis.
Class-D power amplifiers have been widely used as the audio amplifiers in portable devices. The greatest advantage is the high power efficiency of this kind of amplifier, which can improve the operating time and lower the heat dissipation. Nevertheless, the total harmonic distortion in nonlinear amplifiers is much higher than the linear ones. Therefore, the applications of the nonlinear amplifiers are limited to lower-quality audio systems. A class-D audio amplifier system based on a third-ordered analog delta-sigma is proposed and designed in this thesis.
en
dc.description.provenanceMade available in DSpace on 2021-05-20T21:16:37Z (GMT). No. of bitstreams: 1
ntu-100-J96921005-1.pdf: 1904938 bytes, checksum: ac6aacb8e0564e63a417d54c9cb5d589 (MD5)
Previous issue date: 2011
en
dc.description.tableofcontents第一章 緒論 1
1-1 研究動機 1
1-2 論文架構 2
第二章 三角積分調變器(Delta Sigma Modulator)之原理 3
2-1 引言 3
2-1-1 三角積分調變器之原理及特性 3
2-1-2 三角積分調變器之應用 5
2-2 取樣及量化(Sampling and Quantization) 9
2-2-1 奈奎斯特取樣原理(Nyquist Sampling Theory) 9
2-2-2 量化雜訊及模型 11
2-2-3 超取樣原理(Over-Sampling Theory) 14
2-3 雜訊整形(Noise-Shaping) 15
2-3-1 雜訊整形之原理 16
2-3-2 低通一階三角積分調變 17
2-3-3 低通二階三角積分調變 19
2-3-4 低通高階三角積分調變 20
2-3-5 帶通三角積分調變 22
2-4 高階三角積分調變器之架構 23
2-4-1 單級迴路架構(Single-Stage) 23
2-4-2 多級迴路架構(Multi-Stage) 25
2-4-3 離散時間積分器架構(Discrete Time Integration) 27
2-4-4 連續時間積分器架構(Continuous Time Integration) 29
2-5 效能指標 31
2-5-1 訊號雜訊比 31
2-5-2 輸入動態範圍(Dynamic Range) 31
第三章 使用於非整數頻率合成器(Fractional-N Synthesizer)之多級三角積分調變器設計 33
3-1 引言 33
3-1-1 非整數除頻器 33
3-1-2 電路架構 34
3-2 多級雜訊整型1-1-1調變器(MASH 1-1-1)之電路模擬 36
3-2-1 行為模擬 37
3-2-2 加法器 39
3-2-3 累加器 41
3-2-4 誤差消除電路之運算單元 41
3-3 多級雜訊整形調變器模擬結果 42
第四章 使用三角積分調變器之D類音訊放大器之設計 44
4-1 引言 44
4-1-1 D類功率放大器 45
4-1-2 功率放大器效能指標 46
4-2 三階三角積分調變器設計 47
4-2-1 設計考量與規格 47
4-2-2 調變器行為模擬與電路架構 49
4-2-3 全差動運算放大器 53
4-2-4 交換式電容積分器 56
4-2-5 量化器 59
4-2-6 被動加法單元 60
4-2-7 三角積分調變器模擬結果 61
4-3 D類功率放大器設計 66
4-3-1 功率電晶體及驅動控制電路(Gate Driver) 67
4-3-2 全橋式低通濾波器 69
4-3-3 D類功率放大器之開回路模擬結果 71
4-3-4 D類功率放大器閉迴路模擬結果 80
第五章 結論 84
參考文獻. 85
dc.language.isozh-TW
dc.title三角積分調變器與D類音頻放大器設計zh_TW
dc.titleDesign of Delta Sigma Modulator and Class D Audio Amplifieren
dc.typeThesis
dc.date.schoolyear99-1
dc.description.degree碩士
dc.contributor.oralexamcommittee黃育賢,陳昭宏,郭建宏
dc.subject.keyword三角積分調變器,D類音頻放大器,zh_TW
dc.subject.keywordDelta sigma modulator,Class D audio amplifier,en
dc.relation.page89
dc.rights.note同意授權(全球公開)
dc.date.accepted2011-01-26
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept電機工程學研究所zh_TW
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