毫米波與太赫茲之低雜訊放大器與混頻器設計

Abstract

本論文主要針對K/Ka頻段、D頻段與J頻段之無線通訊接收機前端電路進行設計與實現，包含低雜訊放大器與混頻器，並透過實體佈局與晶片量測驗證其高頻特性，分別採用TSMC 90 nm、40 nm與65 nm CMOS製程實現，具備完整的模擬、實作與量測流程。本論文共實現三個電路分別於第二章、第三章與第四章介紹，依序為K/Ka頻段低雜訊放大器、D頻段低雜訊放大器與J頻段混頻器。

第二章實現了K/Ka頻段低雜訊放大器，採用三級共源級串接架構搭配電流重複利用技術降低功耗，並於所有電晶體基極接腳加上電阻後接地，藉此達成更好的雜訊特性，量測結果在25.2 GHz達成22.1 dB峰值增益，3-dB頻寬涵蓋22.6至28.3GHz，雜訊指數為1.94 dB，整體功耗為6.7 mW，晶片面積為0.325 mm²。

第三章實現了D頻段低雜訊放大器，採用四級G\textsubscript{max}-core架構設計，前兩級採用變壓器嵌入網路的技術設計G\textsubscript{max}-core，以獨立閘極與汲極偏壓實現最佳化雜訊性能，後兩級採用傳輸線嵌入網路的技術設計G\textsubscript{max}-core以提升增益，量測結果在138 GHz達成27.2 dB峰值增益與7.1 dB雜訊指數，3-dB頻寬為135至141 GHz，整體功耗為20.1 mW，晶片面積為0.38 mm²。

第四章實現了J頻段雙向混頻器，採用單端被動電阻式架構設計，並使用共源級、共閘級與共汲級測試電路驗證電晶體模型於 300 GHz頻段之準確性，該混頻器電晶體工作於變阻模式，透過閘極偏壓控制混頻操作，量測結果在升頻模式下轉換增益為 –16 dB，降頻模式為–17 dB，3-dB頻寬分別涵蓋256至330 GHz與250至330 GHz，輸出1-dB壓縮點為–26.4 dBm，幾乎無直流功耗，晶片面積為0.295 mm²。

This thesis focuses on the design and implementation of front-end circuits for wireless communication receivers operating in the K/Ka-band, D-band, and J-band. The circuits include low-noise amplifiers (LNAs) and a mixer, which are fabricated and measured to validate their high-frequency performance. The three circuits are implemented using TSMC 90 nm, 40 nm, and 65 nm CMOS processes, respectively, and follow a complete design flow including simulation, layout, and measurement. The three circuits are presented in Chapter 2, Chapter 3, and Chapter 4, corresponding to the K/Ka-band LNA, D-band LNA, and J-band mixer, respectively.

Chapter 2 presents the K/Ka-band LNA, which adopts a three-stage common-source cascade structure with a current-reuse technique to reduce power consumption. The body terminals of all transistors are connected to ground through resistors to improve noise performance. Measurement results show a peak gain of 22.1 dB at 25.2 GHz, with a 3-dB bandwidth covering 22.6 to 28.3 GHz. The noise figure is 1.94 dB, the total power consumption is 6.7 mW, and the chip area is 0.325 mm².

Chapter 3 presents the D-band LNA, which adopts a four-stage G\textsubscript{max}-core architecture. The first two stages employ transformer-embedded G\textsubscript{max}-core structures with independent gate and drain biasing to optimize noise performance, while the latter two stages utilize transmission-line-embedded G\textsubscript{max}-core structures to enhance gain. Measurement results show a peak gain of 27.2 dB and a noise figure of 7.1 dB at 138 GHz, with a 3-dB bandwidth ranging from 135 to 141 GHz. The total power consumption is 20.1 mW, and the chip area is 0.38 mm².

Chapter 4 presents the J-band bidirectional mixer, which adopts a single-ended passive resistive architecture. A series of test circuits including common-source, common-gate, and common-drain configurations are used to validate the accuracy of the transistor model at the 300 GHz frequency range. The mixer operates in resistive mode, with frequency conversion controlled by gate bias. Measurement results show a conversion gain of –16 dB in the up-conversion mode and –17 dB in the down-conversion mode. The 3-dB bandwidths cover 256–330 GHz and 250–330 GHz, respectively. The output 1-dB compression point is –26.4 dBm, and the circuit exhibits virtually no DC power consumption. The chip area is 0.295 mm².