應用於先進封裝之奈米晶粒銅混合直接鍵合與銅打線互連技術研究

Abstract

隨著後摩爾時代來臨，為了超越摩爾定律，半導體產業加速推動了2.5D/3D封裝技術的發展。在半導體製程演進中，銅憑藉其優異的導熱性、電阻率、抗電遷移能力、良好的耐腐蝕性與低廉成本，高性能的銅金屬互連逐漸成為先進製程不可或缺的架構。而特殊微結構的銅-銅金屬直接接合可大幅降低接合溫度與電阻，亦可提升產品可靠度，因此引起諸多先進製程研究團隊的興趣。本論文的研究主題聚焦於特殊微結構之銅金屬在微電子3D-IC封裝技術與功率模組打線接合技術的發展，深入研究低溫微細間距混合鍵合技術與粗銅線超音波接合技術，探討奈米尺寸晶粒的銅金屬(細晶銅、奈米孿晶銅)在高密度異質整合封裝與功率模組應用中的潛力。

第一部分的研究針對3D-IC中低溫細間距奈米晶銅/二氧化矽混合鍵合技術進行深入探討。隨著異質整合封裝的需求日益增加，傳統封裝技術的高溫接合工藝已無法滿足多晶片高密度互連結構的需求。為了克服這一挑戰，本研究提出了使用奈米晶銅作為低溫混合鍵合材料，實現了在250°C以下進行的晶片對晶圓（C2W）鍵合。透過縮小銅金屬的晶粒尺寸，使得晶界面積大幅增加，並利用晶界擴散速度大於晶粒擴散速度之優勢，可有效降低接合溫度。本研究採用了平坦的奈米級細晶銅金屬接點與SiO2介電材料的混合鍵合方式，成功完成了2µm、 3µm及5µm不同尺寸接點的高密度連接，達到了每平方公分6.26 × 10^6個接點的密度。實驗成果顯示，通過奈米晶銅的微結構設計，在接合界面進行的Cu-Cu相互擴散可以在低溫條件下實現高鍵合強度，且其對位精度達到了<0.5µm，最大鍵合強度達到9.01 MPa。此外，經過熱循環測試後，該混合鍵合結構展現了優越的可靠性。綜合以上所述，奈米晶銅的混合鍵合結構不僅能降低封裝過程中的高溫需求、提升鍵合性能，尤其適用於高密度堆疊的晶片封裝，是微電子領域中高密度異質整合技術發展的重要突破。

第二部分的研究則聚焦於功率模組中的粗銅線超音波打線接合技術。傳統的打線接合多使用鋁線、鍍鈀銅線和銀合金線，但這些材料在現今高電流、高電壓的應用需求中易受限於其導電性能與成本效益。為了解決這一問題，本研究針對銅線硬度高、接合負荷大的問題，提出了使用奈米孿晶結構銅金屬化層作為銲墊的創新方法。奈米孿晶銅具有高密度的(111)單一方向奈米級柱狀晶粒，能顯著促進超音波打線接合時的原子擴散反應，加速接合界面的形成，並大幅降低接合負荷。本研究中使用了15mil (380µm)的粗銅線進行超音波接合測試，並比較了不同材料與不同厚度之金屬化層（包括奈米孿晶銅、粗晶銅、奈米孿晶銅+粗晶銅雙層疊構）對接合強度的影響。實驗結果顯示，表層為奈米孿晶銅之銲墊結構可有效提升超音波打線接合的強度、打線機械應力耐受性。此外，透過進一步模擬結果顯示，採用表層奈米孿晶銅(4 µm)與底層粗晶銅(8 µm)為單層奈米孿晶銅(8µm)的 1.28 倍，顯示複合式金屬化層在維持高打線接合強度的同時，亦能有效提升熱循環下的可靠度，為兼顧可靠度與製程可行性的潛力設計。 本論文結合了奈米晶銅在低溫混合鍵合技術與粗銅線超音波接合技術的優勢，展示了其在微電子先進封裝與功率模組應用中的技術創新與突破。透過材料上微結構調整與封裝架構設計優化，不僅可解決高溫、高負荷製程對敏感晶片的影響，還提升了接合的可靠性與強度。這些研究成果不僅拓展了高密度異質整合封裝技術的應用潛力，也為功率模組提供了更具成本效益與高效能的解決方案。

As the post-Moore era approaches, the semiconductor industry has accelerated the development of 2.5D/3D packaging technologies to move past Moore's Law. In this evolution, copper has become an indispensable component of advanced processes due to its excellent thermal conductivity, low electrical resistivity, resistance to electromigration, corrosion resistance, and cost-effectiveness. The copper with the unique microstructure of direct bonding significantly reduces bonding temperature and electrical resistance while improving product reliability, drawing attention among advanced process research teams. This thesis focuses on researching copper metal with specialized microstructures in microelectronics 3D-IC packaging and power module wiring bonding techniques. Specifically, it explores low-temperature, fine-pitch hybrid bonding and ultrasonic bonding of thick copper wires, investigating the potential of nanocrystalline copper (fine-grained copper, nanotwinned copper) in high-density heterogeneous integration and power module applications.

The first part of this study delves into the development of low-temperature, fine-pitch hybrid bonding using nano-grained copper and silicon dioxide for 3D-IC packaging. As the demand for heterogeneous integration continues to grow, traditional high-temperature bonding techniques struggle to meet the requirements of high-density multi-chip interconnections. In order to surpass this challenge, this study proposes using nano-grained copper as a low-temperature hybrid bonding material, achieving chip-to-wafer (C2W) bonding at temperatures below 250°C. By reducing the grain size of copper, the grain boundary area increases, allowing for enhanced grain boundary diffusion, which proceeds faster than grain diffusion, thus decreasing the bonding temperature. This research employed a flat, nano-scale fine-grained copper bonding interface alongside SiO2 dielectric materials, successfully achieving high-density connections with 2µm, 3µm, and 5µm bond pad sizes, resulting in a connection density of 6.26 × 10^6 per cm². Experimental results show that the microstructural design of nano-grained copper enabled effective Cu-Cu interdiffusion at low temperatures, achieving a bonding strength of up to 9.01 MPa with alignment accuracy below 0.5µm. Additionally, the hybrid bonding structure demonstrated excellent reliability after thermal cycling tests. Overall, the hybrid bonding structure using nano-grained copper not only reduces the thermal budget of packaging but also enhances bonding performance, making it a significant breakthrough for high-density, heterogeneous integration in microelectronics.

The second part of the study focuses on ultrasonic bonding of thick copper wires for power modules. Traditional wire bonding materials, such as aluminum, palladium-coated copper, and silver alloy wires, are limited by their conductivity and cost-effectiveness in the trend toward high-current, high-voltage applications. Owning to address the challenges posed by the high hardness and bonding load of copper wires, this study introduces an innovative solution: using a nanotwinned copper layer as the backside metallization. Nanotwinned copper, with its high density of (111)-oriented nano-scale columnar grains, significantly enhances atomic diffusion during ultrasonic bonding, accelerating the formation of the bonding interface and substantially reducing the required bonding load. In this study, ultrasonic bonding tests were conducted using 15 mil (380 µm) thick copper wires, and the effects of various metallization materials and thicknesses including nanotwinned copper (nt-Cu), coarse-grained copper (cg-Cu), and a bilayer structure of nt-Cu and cg-Cu on bonding strength were investigated. Experimental results demonstrated that bonding pads with a nanotwinned copper surface layer significantly enhanced ultrasonic bonding strength. Furthermore, simulation results indicate that the fatigue life of the bilayer structure comprising a 4 µm nt-Cu top layer and an 8 µm cg-Cu bottom layer is approximately 1.28 times that of a single 8 µm nt-Cu layer. This suggests that the composite metallization structure can effectively enhance reliability under thermal cycling while maintaining high bonding strength, offering a promising solution that balances both reliability and manufacturing feasibility. This thesis integrates the advantages of nano-grained copper in low-temperature hybrid bonding and thick copper wire ultrasonic bonding, demonstrating technological innovations and breakthroughs in microelectronics packaging and power module applications. Through precise microstructural design and packaging architecture optimization, this study addresses the challenges posed by high-temperature, high-load processes on sensitive chips, while improving bonding reliability and strength. These research findings expand the potential applications of high-density heterogeneous integration as well as offer cost-effective, high-performance solutions for power modules.