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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/101191完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃俊郎 | zh_TW |
| dc.contributor.advisor | Jiun-Lang Huang | en |
| dc.contributor.author | 廖偉富 | zh_TW |
| dc.contributor.author | Wei-Fu Liao | en |
| dc.date.accessioned | 2025-12-31T16:16:03Z | - |
| dc.date.available | 2026-01-01 | - |
| dc.date.copyright | 2025-12-31 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-12-01 | - |
| dc.identifier.citation | [1] D. Medhat, M. Dessouky and D. Khalil, “Electrostatic Discharge Physical Verifi-cation of 2.5D/3D Integrated Circuits,” 2020 21st International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, 2020, pp. 383-388.
[2] S. M. Alam, R. E. Jones, S. Pozder and A. Jain, “Die/Wafer Stacking with Reciprocal Design Symmetry (RDS) for Mask Reuse in Three-dimensional (3D) Integration Technology,” 2009 10th International Symposium on Quality Electronic Design, San Jose, CA, USA, 2009, pp. 569-575. [3] D. H. Jung et al., “Through Silicon Via (TSV) Defect Modeling, Measurement, and Analysis,” in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 1, 2017, pp. 138-152. [4] S. W. Yoon, “Advanced Package FAB Solutions(APFS) for Chiplet Integration,” 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 3.6.1-3.6.4. [5] Yuan-Kai Ho and Y.-W. Chang, “Multiple Chip Planning for Chip-Interposer Codesign,” 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, USA, 2013, pp. 1-6. [6] W.-H. Liu, Min-Sheng Chang and T.-C. Wang, “Floorplanning and Signal Assign-ment for Silicon Interposer-Based 3D ICs,” 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2014, pp. 1-6. [7] G. -S. Chen, P. -J. Yen, J. -L. Huang, K. Lu, C. -C. Peng and Y. -S. Chang, "Repair and Timing-Aware Signal Path Assignment for Inter-Die Interconnects," 2025 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), Hsinchu, Taiwan, 2025. [8] Y. Lee, D. Han and S. Kang, “TSV Built-In Self-Repair Architecture for Improving the Yield and Reliability of HBM,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 4, 2023, pp. 578-590. [9] B. Meindl and M. Templ, “Analysis of Commercial and Free and Open Source Solvers for the Cell Suppression Problem.” Tansaction on Data Privacy, vol. 6, no. 2, 2013, pp. 147-159. [10] D. P. Seemuth, A. Davoodi and K. Morrow, “Automatic Die Placement and Flexible I/O Assignment in 2.5D IC Design,” Sixteenth International Symposium on Quality Electronic Design, Santa Clara, CA, USA, 2015, pp. 524-527. [11] J.-M. Lin, T.-L. Tsai and T.-C. Tsai, “Multilevel Fixed-Outline Component Place-ment and Graph-Based Ball Assignment for System in Package,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 9, 2023, pp. 1308-1319. [12] D. P. Seemuth and K. Morrow, “Automated Multi-Device Placement, I/O Voltage Supply Assignment, and Pin Assignment in Circuit Board Design,” 2013 International Conference on Field-Programmable Technology (FPT), Kyoto, Japan, 2013. [13] L. Jiang, Q. Xu and B. Eklow, “On effective TSV repair for 3D-stacked ICs,” 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 2012, pp. 793-798. [14] T. Ni, D. Liu, Q. Xu, Z. Huang, H. Liang and A. Yan, “Architecture of Cobweb-Based Redundant TSV for Clustered Faults,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 7, 2020, pp. 1736-1739. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/101191 | - |
| dc.description.abstract | 隨著高效能運算的興起以及跨晶片連線數量的急遽增加,3D IC封裝已成為整合技術的關鍵。然而,大量的互連也帶來更高的故障風險,使得互連修復成為不可或缺的技術。
本論文提出一種專為3D IC跨晶片修復鏈設計的訊號指派方法。該方法首先利用最小成本最大流(MCMF)演算法產生初始連線解,接著結合模擬退火(SA)針對時序要求進行優化。 與僅針對功能性訊號指派的過往研究不同,本方法同時考慮訊號的功能與修復路徑、滿足時序要求以及總線長最小化。實驗結果顯示,與整數線性規劃(ILP)相比,所提出方法在執行時間上有超過數千倍的加速,且維持高修復能力與低連線成本,展現良好的可擴展性,適用於實際3D IC修復應用場景。 | zh_TW |
| dc.description.abstract | With the rise of high-performance computing and the rapid increase in inter-die connections, 3D IC packaging has become a key integration technology. However, the large number of interconnects also introduces higher risk of faults, making interconnect repair a necessity technique.
This paper proposes a signal assignment method specifically designed for inter-die repair chains in 3D ICs. The method first generates an initial routing solution using the min-cost max-flow (MCMF) algorithm, and then applies simulated annealing (SA) to optimize for timing requirements. Unlike previous studies that focus solely on functional signal assignment, the proposed method simultaneously considers functional and repair paths, satisfies timing constraints, and minimizes total wirelength. Experimental results show that compared to integer linear programming (ILP), the proposed method achieves over 1000 times speedup in runtime while maintaining high repairability and low routing cost. This demonstrates strong scalability and practical applicability in real-world 3D IC repair scenarios. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-12-31T16:16:03Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-12-31T16:16:03Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 致謝 i
摘要 ii Abstract iii Contents iv List of Figures vii List of Tables ix Chapter 1 Introduction 1 1.1 Overview of 2.5D and 3D IC Packaging 1 1.2 Importance of Interconnect Repair in 3D ICs 2 1.3 Cross-Die Signal Path in 3D ICs 3 1.4 Interconnect Repair Architecture 4 1.4.1 Overview of Interconnect Repair Architecture 4 1.4.2 The Signal-Shifting Repair Technique 5 1.5 Related Works 6 1.6 Motivation 8 1.7 Contribution 8 1.8 Organization of Thesis 9 Chapter 2 Preliminaries 10 2.1 Functional Path, Repair Path, and Repair Chain Length 10 2.2 Repair-Aware Signal Assignment for Cross-Die Interconnects 11 2.3 Half-Perimeter Wire Length (HPWL) 13 2.4 Min-Cost Max-Flow (MCMF) 13 2.5 Simulated Annealing 15 Chapter 3 Proposed Methodology 17 3.1 Problem Formulation 17 3.2 Overview of the Proposed Method 20 3.3 Initial Solution: Min-Cost Max-Flow 20 3.3.1 Min-Cost Max-Flow for Bipartite Matching 20 3.3.2 The Proposed Method (Min-Cost Max-Flow) 21 3.3.3 Connect SMUX to BUMP via Min-Cost Max-Flow 23 3.3.4 Connect BUMP to BMUX via Min-Cost Max-Flow 25 3.3.5 Connect SRC to SMUX and BMUX to DES via Min-Cost Max-Flow 26 3.3.6 Connect All Repair Path Level 0 via Min-Cost Max-Flow 27 3.3.7 Connect All Repair Path Level N via Min-Cost Max-Flow 29 3.4 Optimization via Simulated Annealing 30 Chapter 4 Experimental Results 37 4.1 Experiment Setup 37 4.2 Evaluate the Capability of Min-Cost Max-Flow Combined with Simulated Annealing 38 4.2.1 Analyze the Impact of the Number of Bumps on Experimental Results 39 4.2.2 Analyze the Impact of Timing Budget Range on Experimental Results 41 4.2.3 Analyze the Impact of the Maximum Distance Between the SRC-DES Pair 43 4.2.4 Analyze the Impact of the Minimum Distance Between Components 45 4.2.5 Analyze the Impact of the Redundant Ratio 47 4.3 Evaluate the Capability of Min-Cost Max-Flow 49 4.3.1 Analyze the Impact of the Number of Bumps on Experimental Results 50 4.3.2 Analyze the Impact of Data Pruning on Experimental Results 51 4.3.3 Comparison Between ILP and the Proposed Method (Using Only Min-Cost Max-Flow and Without Data Pruning) 53 Chapter 5 Conclusion and Future Work 57 5.1 Conclusion 57 5.2 Future Work 57 References 59 | - |
| dc.language.iso | en | - |
| dc.subject | 三維積體電路 | - |
| dc.subject | 跨晶片訊號 | - |
| dc.subject | 訊號指派 | - |
| dc.subject | 最小成本最大流 | - |
| dc.subject | 模擬退火 | - |
| dc.subject | 修復鏈 | - |
| dc.subject | 3D Integrated Circuits | - |
| dc.subject | Inter-die Signal | - |
| dc.subject | Signal Assignment | - |
| dc.subject | Min-Cost Max-Flow | - |
| dc.subject | Simulated Annealing | - |
| dc.subject | Repair Chain | - |
| dc.title | 三維積體電路中具時序考量的功能與修復路徑訊號指派方法:結合最小成本最大流與模擬退火法 | zh_TW |
| dc.title | Timing-Aware Signal Assignment for Functional and Repair Paths in 3D ICs via Min-Cost Max-Flow and Simulated Annealing | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 114-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 張益興;彭中靖;李進福 | zh_TW |
| dc.contributor.oralexamcommittee | Yi-Shing Chang;Chung-Ching Peng;Jin-Fu Li | en |
| dc.subject.keyword | 三維積體電路,跨晶片訊號訊號指派最小成本最大流模擬退火修復鏈 | zh_TW |
| dc.subject.keyword | 3D Integrated Circuits,Inter-die SignalSignal AssignmentMin-Cost Max-FlowSimulated AnnealingRepair Chain | en |
| dc.relation.page | 60 | - |
| dc.identifier.doi | 10.6342/NTU202504705 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2025-12-01 | - |
| dc.contributor.author-college | 重點科技研究學院 | - |
| dc.contributor.author-dept | 積體電路設計與自動化學位學程 | - |
| dc.date.embargo-lift | N/A | - |
| 顯示於系所單位: | 積體電路設計與自動化學位學程 | |
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| ntu-114-1.pdf 未授權公開取用 | 2.1 MB | Adobe PDF |
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