針對工程變更命令整合式考量電壓降之時序與時序感知之電壓降最佳化結合機器學習式電壓降預測

Abstract

本文提出一個整合式考量電壓降之時序最佳化與感知時序之電壓降最佳化流程，並結合電壓降預測器。所提出的流程將電壓降感知時序最佳化器與時序感知電壓降最佳化器耦合，使最佳化過程能同時考量電壓降與時序之間的交互影響。接著，我們利用一個快速的機器學習式預測器，在每次最佳化迭代後快速估計電壓降，從而實現電壓降最佳化器與時序最佳化器之間的高效切換。此外，我們提出特徵近似 (Feature Approximation) 方法，以進一步加速電壓降預測器的推論時間。 在兩個 7 奈米電路設計上，所提出的流程能同時達成時序收斂，並消除至少90.6% 的電壓降違規。透過特徵近似技術，整體流程的執行時間可加速 67%。我們的最佳化流程亦成功應用於一個含 945k 個 cell、具有 7,578 個電壓降違規的大型設計，並於 3 小時內完成，展現了其實用性。

This paper presents an integrated IR-Informed Timing and Timing-Aware IR Optimization flow with an IR-drop predictor, targeted for the Engineering Change Order (ECO) stage. The proposed flow considers the mutual impact between IR-drop and timing during optimization. Then, we leverage a fast ML-based IR predictor to quickly estimate the IR-drop after each iteration of optimization, which enables fast switching between the IR optimizer and timing optimizer. The proposed Feature Approximation speed up the inference time of the IR-drop predictor. On two 7nm designs, the proposed flow closes timing and eliminates at least 90.6% of IR-drop violations. The Feature Approximation achieves 67% speed up in the runtime of the overall flow. Our optimization flow can be applied to a 945k-cell design with 7,578 IR-drop violations within 3 hours, demonstrating its practicality.