http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/162 Fri, 17 Apr 2026 08:56:13 GMT 2026-04-17T08:56:13Z http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71015 標題: 黑磷雙閘極電晶體開發及研究; Development and Investigation of the Dual-gate Black Phosphorus Field-Effect Transistor 作者: Kai-Lin Fan; 范鎧麟 摘要: 在本論文中，我們提出一個方法解決在製作黑磷電晶體元件時，在通道與介電層會出現的介面問題。介面問題的主要原因是因為黑磷表面缺少未鍵結電子對(Lack of dangling bonds)，而現今解決方式主要分為兩種，第一種是使用同樣為二維材料的六方-氮化硼(Hexagonal Boron Nitride, h-BN)來取代傳統介電層(Al2O3, HfO2, etc.)；第二種是使用傳統介電層來完成元件。 首先，我們以h-BN當作介電層來製作黑磷電晶體。我們發現在使用氮化硼之後，可以觀察到元件載子遷移率的提升以及遲滯的下降。因為氮化硼表面同樣缺少未鍵結電子對，可以有效地減少通道表面散射。然而，h-BN厚度不易控制，並不適合用於往後的元件製作(top-gate FET, RF device, etc.)， 因此我們改用傳統的Al2O3來當作我們介電層。 Al2O3的成長是使用原子層沉積技術(Atomic layer deposition, ALD)。藉由調整成長參數，我們成功在黑磷上成長具有高品質的Al2O3。我們發現ALD的高溫成長過程，對黑磷電晶體的鍺金屬接點有退火的效果，透過EDX的分析我們可以發現鍺擴散進入黑磷的情形。除此之外，我們使用Raman並分析h-BN及Al2O3於大氣環境中對黑磷的保護程度。 透過高品質Al2O3的成長，我們不僅成功製成黑磷上閘極電晶體，也藉由下閘極的調變來得到黑磷雙閘極電晶體。我們藉由黑磷雙閘極電晶體的分析可以得到Al2O3的介電常數為9.6，此一結果高出許多先前的研究。我們也分析了黑磷雙閘極電晶體的控制機制，以及藉由雙閘極電晶體的結構，來達成黑磷的能隙調變。 綜合以上結果，我們得到了於黑磷上成長高品質Al2O3的方法，解決了黑磷通道和介電層的介面問題，並完成了黑磷雙閘極電晶體的量測與分析，進一步了解其控制機制及應用。; In this paper, we propose a method to solve the interface problem that occurs in the channel and dielectric layer when making black phosphorus field-effect transistor. The main reason for the interface problem is that the black phosphorus lacks of dangling bonds on its surface. Nowadays, there are two main solutions in this case. The first one is to replace the traditional dielectric layer (Al2O3, HfO2, etc.) with Hexagonal Boron Nitride (h-BN), which is also a two-dimensional material. The second one is using traditional dielectric layers to complete the components. First, we use h-BN as dielectric layer to make BP field-effect transistor. We have found that after the use of boron nitride, an increase in the mobility and a decrease in hysteresis can be observed. Because the boron nitride surface also lacks dangling bonds, BP channel surface scattering can be effectively reduced. However, h-BN thickness is not easy to control and is not suitable for top-gate FET (RF device, etc.), so we use traditional Al2O3 as our dielectric layer. Al2O3 is grown by Atomic layer deposition (ALD). By adjusting the growth parameters, we can grow high-quality Al2O3 on black phosphorus. After the growth of Al2O3, we found that the high temperature growth process of ALD has an annealing effect on the Germanium metal contact of the black phosphorus. Through the analysis of EDX, we can find that Germanium diffuses into black phosphorus. Furthermore, we used Raman to analyze the degree of protection of black phosphorus by h-BN and Al2O3 in the atmosphere. Finally, through the growth of high-quality Al2O3, we not only succeeded in making black phosphorus top-gate field-effect transistor, but also black phosphorus dual-gate gate transistor by the modulation of the bakc gate. We obtain a dielectric constant of 9.6 for Al2O3 by analysis of a black phosphorus dual-gate transistor. The dielectric constant result is much higher than many previous studies. We also analyzed the control mechanism of the black phosphorus dual-gate transistor and achieved the energy band gap modulation of black phosphorus. Based on the above results, we obtained a method for growing high-quality Al2O3 on black phosphorus, and solved the interface problem of black phosphorus channel and dielectric layer. We also completed the measurement and analysis of black phosphorus dual-gate transistor, and further understood its control mechanism and application. Mon, 01 Jan 2018 00:00:00 GMT http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71015 2018-01-01T00:00:00Z http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71192 標題: 鰭狀砷化銦鎵高載子遷移率電晶體及負電容材料之研究; Investigation of the InGaAs Fin Structure High Electron Mobility Transistors and Negative Capacitance Material 作者: Shun-Cheng Yang; 楊舜丞 摘要: 以摩爾定律做為開頭，快速回顧半導體過去近50年的發展，瞭解前人於每個技術節點上所遇到的問題以及克服之方法，並簡述未來可能應用之半導體材料及技術，包括三五族電晶體及負電容電晶體。 本論文第一部分簡介高載子遷移率電晶體與其介面特性，利用金氧半電容結構萃取三五族化合物與氧化物之介面缺陷密度，驗證硫化銨溶液確實能降低介面缺陷密度，並比較不同條件之硫化銨表面鈍化，得一最佳化條件，接著將此鈍化條件導入鰭式砷化銦鎵高載子遷移率電晶體之製程中，觀察硫化銨表面鈍化對於電晶體特性之影響。 第二部分以製程技術成功製作出鰭式金屬氧化物半導體砷化銦鎵高載子遷移率電晶體，利用原子層沉積技術於閘極中加入10奈米氧化鋁，其能有效抑制閘極漏流，另外，藉由鰭寬度的微縮我們成功製作出常關式高載子遷移率電晶體，達到低功率消耗的需求，並提出一套理論解釋臨界電壓調變之機制。 第三部分，首先簡述鐵電材料以及負電容特性之應用，接著利用high-k材料氧化鉿搭配鐵電材料氧化鋯的形式製作出負電容元件，驗證電容放大特性，並比較不同厚度的氧化物組合造成電容放大倍率之差異。; Starting with Moore's law, we quickly review the development of semiconductors in the past 50 years, and understand the problems encountered by predecessors at each technology node along with the methods to overcome them. Also, we briefly describe the semiconductor materials and technologies that may be applied in the future, including III-V transistors and negative capacitance transistors. The first part of this thesis introduces the characteristics of high-electron-mobility transistors (HEMTs) and its interface. We fabricated metal-oxide-semiconductor capacitor structure to extract interface traps density between III-V compound semiconductors and oxide layer. It was verified that the ammonium sulfide solution can reduce the interface traps density. We also compared different passivation conditions to obtain an optimized parameter. The optimized passivation condition was introduced into the process of the fin-structured InGaAs HEMTs, and the effect of surface passivation on the transistor was discussed. In the second part, the fin structure metal-oxide-semiconductor HEMTs (Fin-MOSHEMTs) was successfully fabricated by process techniques. The atomic layer deposition technique was used to add 10 nanometer Al2O3 into the gate stack, which can effectively suppress the gate leakage. In addition, by scaling of fin width, we successfully fabricated normally-off HEMTs to meet the demand for low power consumption. Furthermore, we proposed a theory to explain the mechanism of threshold voltage modulation. The third part of this thesis, we briefly introduce the ferroelectric materials and the application of negative capacitance characteristics. The high-k material HfO2 was combined with the ferroelectric material ZrO2 to form a negative capacitance device, which is used to verify the capacitance amplification characteristics. Also, we compared the capacitance amplification results between the different thickness combination of the oxide layer. Mon, 01 Jan 2018 00:00:00 GMT http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71192 2018-01-01T00:00:00Z http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71012 標題: 高頻氮化鋁鎵/氮化鎵高電子遷移率晶體之研究; Investigation of the High Frequency AlGaN/GaN HEMTs 作者: Kai-Chieh Hsu; 許凱傑 摘要: 本篇論文中，我們採用於高阻矽基板上的氮化鋁鎵/氮化鎵異質接面結構製作高頻HEMT元件，並分析其直流與高頻特性。 論文首先針對元件的直流特性進行分析，我們利用電子束技術成功製作出閘極線寬150奈米的元件，最高將gm推至247.4 mS/mm，並針對不同的幾何尺寸進行探討 接著為了分析元件的高頻特性，我們利用ADS模擬軟件建立一套小訊號等效電路模型，幫助我們了解元件內部小訊號參數的影響，同時也針對不同幾何尺寸的元件進行分析，最佳元件fT與fmax於汲極偏壓30V下，分別為25.86 GHz和99.26 GHz。 最後為了進一步提升截止頻率，我們開發T型閘極製程，其目的為降低Rg電阻，使fmax能繼續往上提升。; In this thesis, we fabricate the RF device with AlGaN/GaN heterostructures on 4-inch silicon substrate and analyze their electrical characteristics. First, we analyze the DC chatacteristics of device. We successfully use E-beam lithography technology to define gate length about 150nm. The small gate length leads high transconductance(gm) about 247.4 mS/mm. We also discuss different geometric device in this part. For high frequency characteristics, we build the small-signal model by ADS and simulate each component in the circuit. The best device fT and fmax are 25.26GHz and 99.26 GHz respectively in VD=30V. Finally, in order to push up the fmax value, we develope the T-shaped gate process. In this structure, the wide upper layer increases the croess-sectional area of the gate, thus reducing gate resistance. Mon, 01 Jan 2018 00:00:00 GMT http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71012 2018-01-01T00:00:00Z http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/9519 標題: 高頻CMOS鎖相迴路之設計與實現; Design and Implementation of High-frequency CMOS Phase-locked Loops 作者: Sin-Jhih Li; 黎信志 摘要: 本篇論文主題主要在介紹高頻鎖相迴路的設計與實作。論文中討論了數個方法以改善在高頻鎖相迴路中時脈擾動的情形。論文共分為六個章節，首先第一章對此篇論文作概略性的介紹，第二章則回顧鎖相迴路的背景知識。 第三章提出了一個使用多重相位控制的鎖相迴路架構。藉由此架構可有效抑制壓控震盪器控制電壓上來自參考時脈的週期性擾動，進而減少時脈鎖定時的擾動現象。此迴路架構使用了0.18-μm標準互補式金氧半導體製程加以實現，同時量測結果也會於本章呈現。 第四章將實現一個雙迴路的鎖相迴路架構。此架構可等效上減少迴路濾波器所需要的電容面積，故有助於單晶積體電路的整合。由於來自晶片外的元件雜訊減少了，時脈鎖定時的雜訊擾動現象也能因此有所改善。此鎖相迴路設計使用了0.18-μm標準互補式金氧半導體製程實作並且加以量測。 第五章將討論一個30-GHz的鎖相迴路設計。此設計採用了改良式的Colpitts壓控震盪器以減少壓控震盪本身所產生雜訊並使用了regenerative除頻器來增加如此高速下時脈信號的除頻範圍。此章將詳述此30-GHz鎖相迴路之設計流程與模擬結果。; This thesis illustrates the implementation of the high frequency phase-locked loops (PLLs). In order to reduce the output jitter, several strategies are presented, which are suitable for high speed PLL design. The thesis is organized as six chapters. The first chapter is the introduction. In chapter 2, the background knowledge for the PLL design is overviewed. In chapter 3, a PLL with multi-phase control architecture is proposed. Since the proposed architecture effectively suppresses the ripple of the controlled voltage, the jitter resulted from the reference feedthrough is decreased. The circuit is implemented with 0.18-μm CMOS technologies and the measured resulted is also included in this chapter. In chapter 4, a PLL with a compact loop filter is presented. The presented architecture is well suited for the implementation of fully integrated PLLs since the required capacitance in the loop filter can be substantially reduced. The jitter performance will be improved because of the absence of offchip components. The circuit is also realized with 0.18-μm CMOS process and the measured resulted is also included in this chapter. In chapter 5, a PLL operated at 30-GHz is designed and simulated. The modified Colpitts VCO is adopted for the reduction of the VCO noise. A regenerative frequency divider is also employed to widen the dividable range at such high frequency. The design process and the simulation results will be illustrated in this chapter. Tue, 01 Jan 2008 00:00:00 GMT http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/9519 2008-01-01T00:00:00Z