請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/56574
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 胡振國(Jenn-Gwo Hwu) | |
dc.contributor.author | Xing-You Lin | en |
dc.contributor.author | 林星佑 | zh_TW |
dc.date.accessioned | 2021-06-16T05:35:38Z | - |
dc.date.available | 2014-08-21 | |
dc.date.copyright | 2014-08-21 | |
dc.date.issued | 2014 | |
dc.date.submitted | 2014-08-12 | |
dc.identifier.citation | References
[1] W. Shockley: ‘Circuit Element Utilizing Semiconductor Material’. U.S. Patent 2269347, September 25, 1951 [2] Donald A. Neamen, “Semiconductor Physics and Devices: Basic Principles,” 3rd edition, published by McGraw-Hill, 2003. [3] D. Kahng and M. M. Atalla, 'Silicon-Silicon Dioxide Field Induced Surface Devices,' IRE Solid-State Devices Res. Conf., Carnegie Institute of Technology, Pittsburgh, Pa., 1960. [4] G. E. Moore, “Progress in Digital Integrated Circuit” in IEDM Tech. Dig, p.11,1975 [5] Takeda, E., 'Hot-carrier effects in submicrometre MOS VLSIs,' Solid-State and Electron Devices, IEE Proceedings I , vol.131, no.5, pp.153,162, October 1984 [6] Chamberlain, Savvas G.; Ramanan, S., 'Drain-induced barrier-lowering analysis in VSLI MOSFET devices using two-dimensional numerical simulations,' Electron Devices, IEEE Transactions on , vol.33, no.11, pp.1745,1753, Nov 1986 [7] Chan, T.-Y.; Chen, J.; Ko, P.-K.; Hu, C., 'The impact of gate-induced drain leakage current on MOSFET scaling,' Electron Devices Meeting, 1987 International , vol.33, pp.718,721, 1987 [8] Numata, T.; Takagi, S., 'Device design for subthreshold slope and threshold voltage control in sub-100-nm fully depleted SOI MOSFETs,' Electron Devices, IEEE Transactions on , vol.51, no.12, pp.2161,2167, Dec. 2004 [9] Barin, N.; Braccioli, M.; Fiegna, C.; Sangiorgi, E., 'Scaling the high-performance double-gate SOI MOSFET down to the 32 nm technology node with SiO2-based gate stacks,' Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, pp.609,612, 5-5 Dec. 2005 [10] Khakifirooz, A.; Antoniadis, D.A., 'Transistor Performance Scaling: The Role of Virtual Source Velocity and Its Mobility Dependence,' Electron Devices Meeting, 2006. IEDM '06. International, pp.1,4, 11-13 Dec. 2006 [11] Lee, J.C.; Cho, H. J.; Kang, C. S.; Rhee, S.; Kim, Y. H.; Choi, R.; Kang, C. Y.; Choi, C.; Abkar, M., 'High-k dielectrics and MOSFET characteristics,' Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International , pp.4.4.1,4.4.4, 8-10 Dec. 2003 [12] International Technology Roadmap for Semiconductor (ITRS). [Online]. http:www.itrs.net/reports.html [13] Wei, Chia-Yu; Adriyanto, F.; Lin, Yu-Ju; Li, Yu-Chang; Tong-Jyun Huang; Chou, Dei-Wei; Yeong-Her Wang, 'Pentacene-Based Thin-Film Transistors With a Solution-Process Hafnium Oxide Insulator,'Electron Device Letters, IEEE , vol.30, no.10, pp.1039,1041, Oct. 2009 [14] Blomme, P.; De Vos, J.; Akheyat, A.; Haspeslagha, L.; Houdt, J.V.; De Meye, K., 'Scalable Floating Gate Flash Memory CellWith Engineered Tunnel Dielectric and High-K (Al2O3) Interpoly Dielectric,' Non-Volatile Semiconductor Memory Workshop, 2006. IEEE NVSMW 2006. 21st , pp.52,53, 12-16 Feb. 2006 [15] Chang, S. W.; Chia-Lin Chen; Wang, C. J.; Wu, K., 'A new TDDB lifetime bi-model for eDRAM MIM capacitor with ZrO2 high-k dielectrics,' Physical and Failure Analysis of Integrated Circuits, 2008. IPFA 2008. 15th International Symposium on, pp.1,4, 7-11 July 2008 [16] M. Houssa, L. Pantisano, L.-A. Ragnarsson, R. Degraeve, T. Schram, G. Pourtois, S. De Gendt, G. Groeseneken, M.M. Heyns, Electrical properties of high-κ gate dielectrics: Challenges, current issues, and possible solutions, Materials Science and Engineering: R: Reports, Volume 51, Issues 4–6, 30 April 2006, Pages 37-85, ISSN 0927-796X, 10.1016/j.mser.2006.04.001. [17] Moon-Sig Joo; Jin Cho, Byung; Balasubramanian, N.; Dim-Lee Kwong, 'Stoichiometry dependence of Fermi-level pinning in fully silicided (FUSI) NiSi gate on high-K dielectric,' Electron Device Letters, IEEE , vol.26, no.12, pp.882,884, Dec. 2005 [18] Ito, S.; Noguchi, K.; Horiuchi, T.; Clemens, J.T., 'Limitation of post-metallization annealing due to hydrogen blocking effect of multilevel interconnect,' VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on , pp.182,183, 9-11 June 1998 [19] Robert Chau, Justin Brask, Suman Datta, Gilbert Dewey, Mark Doczy, Brian Doyle, Jack Kavalieros, Ben Jin, Matthew Metz, Amlan Majumdar, Marko Radosavljevic, Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology, Microelectronic Engineering, Volume 80, 17 June 2005, Pages 1-6, ISSN 0167-9317, 10.1016/j.mee.2005.04.035. [20] Han, J.-P.; Vogel, E.M.; Gusev, E. P.; D'Emic, C.; Richter, C.A.; Heh, D. W.; Suehle, J.S., 'Energy distribution of interface traps in high-k gated MOSFETs,' VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on , pp.161,162, 10-12 June 2003 [21] L. Pereira, P. Barquinha, E. Fortunato, R. Martins, D. Kang, C.J. Kim, H. Lim, I. Song, Y. Park, High k dielectrics for low temperature electronics, Thin Solid Films, Volume 516, Issue 7, 15 February 2008, Pages 1544-1548, ISSN 0040-6090, 10.1016/j.tsf.2007.03.088. [22] D. M. Hausmann, R.G. Gordon, J. Cryst. Growth 249 2003 251 [23] In-Sung Park; Kyoung-min Ryu; Jaehack Jeong; Jinho Ahn, 'Dielectric Stacking Effect of and in Metal–Insulator–Metal Capacitor,' Electron Device Letters, IEEE , vol.34, no.1, pp.120,122, Jan. 2013 [24] Jung-Chin Chiang; Hwu, Jenn-Gwo, Low temperature (< 400 oC) Al2O3 ultrathin gate dielectrics prepared by shadow evaporation of aluminum followed by nitric acid oxidation,” ' Applied Physics Letters , vol.90, no.10, pp.102902,102902-3, Mar 2007 [25] Yang, K.; Ya-Chin King; Chenming Hu, 'Quantum effect in oxide thickness determination from capacitance measurement,' VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on , pp.77,78, 14-16 June 1999 [26] SK Ghandhi, VLSI fabrication Principles, 2nd ed. New York: Wiley, 1994, pp. 561-564 [27] X. Garros, C. Leroux, and J. L. Autran, 'An efficient model for accurate capacitance-voltage characterization of high-k gate dielectrics using a mercury probe', Electrochem. Solid-State Lett., vol. 5, no. 3, pp.F4 -F6 2002 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/56574 | - |
dc.description.abstract | 本論文為探討以堆疊結構成長高介電常數閘極介電層之電流與電容特性比較。首先在 P 型基板上利用純水陽極氧化技術於室溫生長超薄二氧化矽作為初始緩衝層,經退火處理後再利用濺鍍法鍍上鉿薄膜並利用硝酸氧化技術形成氧化鉿。
第一個實驗我們比較三種不同介電層形式的樣本,分別是純二氧化矽氧化層(等效厚度 EOT 約 2.1nm)、二氧化矽堆疊一層氧化鉿(~2.9nm)以及二氧化矽堆疊兩層氧化鉿(~3.8nm)。我們發現隨著堆疊層數的增加,其在負偏壓情況下的閘極漏電流呈現下降趨勢,比較經過連續兩次氧化鉿堆疊製備前後元件特性,其閘極漏電流大幅下降了 7 個數量級之多,也具備良好的電容電壓特性曲線。考慮去除厚度對電流的影響因素後,我們比較了相同等效電場下的漏電流,發現堆疊結構的確大幅改善了氧化層的品質。我們推斷在堆疊結構下的元件具有隨意分散的介面缺陷密度使得氧化層本質漏電流路徑可被有效的阻擋。對照電容電壓特性曲線,發現介面缺陷密度會隨堆疊層數增加而增加。分析三種樣品的均勻性,以固定電流下的電壓變化來看,發現其均勻性也隨著堆疊層數增加而更加改善。這說明了氧化層品質可以藉由分層堆疊方式將其單層不均勻性的影響減到最小。接下來的實驗,我們將這三片樣本放置在 380 °C氮氣環境下進行熱退火,此舉可有效去除介電層中的氫或其他帶電的離子。經過熱退火後,除了純二氧化矽介電層的樣本外,其他樣本的平帶電壓與介面陷阱密度都大幅減少,代表熱退火對於修復高介電常數介電層的品質來說是必要的。 | zh_TW |
dc.description.abstract | In this work, the electrical and capacity characteristics of HfO2 high-k gate dielectric in tandem structure are investigated. The ultrathin interfacial SiO2 grown on p-type Si substrate was prepared by anodization in D.I water followed by post oxidation anneal. The sputtered hafnium film was oxidized by diluted nitric acid (HNO3) to form the HfO2 dielectric layer. First, we compared three kinds of MOS capacitors, i.e., the pure SiO2 dielectrics (EOT~2.1nm), one HfO2 dielectric stacked on SiO2 dielectrics (EOT~2.9nm) and two HfO2 dielectrics stacked on SiO2 dielectrics (EOT~3.8nm). We found that the gate leakage current in negative voltage bias decreased with the stacked layer added more. The gate leakage current value in tandem structure sample was scaled down about seven orders difference compared to the sample without tandem structure fabrication and it still showed good electrical and capacitance characteristics. Excluding the effect of dielectric thickness, we found that the dielectrics fabricated in tandem structure obviously improved the quality of oxide dielectrics according to the leakage current of the equivalent electric field. We proposed that the devices in tandem structure have random distributed defect which could block the path of intrinsic current conduction. The fact that the interfacial defect density became more when stacked layer was added was observed from the capacitance voltage characteristic curve. The uniformity of these three samples also improved as the stacked layer added in terms of the voltage at specific current value, which illustrated that this separated stacked fabrication could largely reduce the influence of nonuniformity in each monolayer. In the following experiment, these three samples were annealed in 380 ℃ N2 ambient which could eliminate the hydrogen and other ions. Through this annealing, the flat band voltage and interfacial defect density was largely decreased in all samples except the pure SiO2 sample. It proved that the post metallization anneal is necessary for high-k dielectric to repair. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T05:35:38Z (GMT). No. of bitstreams: 1 ntu-103-R00943050-1.pdf: 4406579 bytes, checksum: 3d835fb395a57fd53477295492c3c251 (MD5) Previous issue date: 2014 | en |
dc.description.tableofcontents | CONTENTS
口試委員審定書……………………………………………………………I 誌謝……..………………………………………………………..……...III 摘要…………………………………………………………………...IV ABSTRACT..………………………………………………………….......V CONTENTS.…………………………………….………..……...VII TABLE CAPTIONS.……………………………………………….IX FIGURE CAPTIONS...……………………………….……………...….X Chapter 1 Introduction…..……………………………………………..…………...…1 1-1 Motivation……………….………………………………………………………….…1 1-2 High-k Gate Dielectrics….…………………………………………….……………...3 1-5 About This Work………….…………………………………………………………...5 Chapter 2 Characteristics of HfO2 and SiO2 Tandem Structure Dielectrics 2-1 Introduction………………..……………………………………………….………....9 2-2 Experimental………………..…………………………………………….…….........11 2-3 Results and Discussion………..………………………………………,…………….13 2-3-1 Capacitance-Voltage Characteristics…………………………………………..13 2-3-2 Current Density-Voltage Characteristics……………………………………....14 2-3-3 Constant Voltage Stress Test…………………………………………………..14 2-3-4 Time Zero Dielectric Breakdown Test………………………………………...15 2-3-5 Quality and Uniformity of MOS devices……………………………………...16 2-4 Summary…………………………………………………………………………….17 Chapter 3 Characteristics of HfO2/SiO2 Tandem Structure Dielectrics with Post Metalization Annealing…………………………………………………....25 3-1 Introduction ………………………………………………………………………….26 3-2 Experimental…………………………………………………………………………27 3-3 Results and Discussion………………………………………………………………28 3-3-1 TEM Results of HfO2/SiO2 Tandem Structure Dielectrics………………….....28 3-3-2 Capacitance-Voltage Characteristics…………………………………………..29 3-3-3 Current Density-Voltage Characteristics………………………………………30 3-3-4 Current Conduction Mechanism ……………………………………………...32 3-3-5 Time Zero Dielectric Breakdown Test………………………………………...33 3-3-6 Quality and Uniformity of HfO2/SiO2 Tandem Structure Dielectrics………....34 3.4 Summary……………………………………………………………………………..35 Chapter 4 Conclusions and Suggestions………………………………………………44 4-1 Conclusions………………………………………………………………………….44 4-2 Suggestions for the Future Work…………………………………………………….46 References……………………………………………………………………….………48 | |
dc.language.iso | zh-TW | |
dc.title | 以硝酸氧化備製中堆疊高介電常數氧化鉿閘極介電層之金氧半電容元件特性研究 | zh_TW |
dc.title | Investigation of HfO2 High-k Gate Dielectrics in Tandem Structure Fabricated by Nitric Acid Oxidation for MOS Devices | en |
dc.type | Thesis | |
dc.date.schoolyear | 102-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 鄭晃忠(Huang-Chung Cheng),田維誠(Wei-Cheng Tian),吳肇欣(Chao-Hsin Wu) | |
dc.subject.keyword | 金氧半電容元件,高介電常數材料,堆疊結構, | zh_TW |
dc.subject.keyword | MOS devices,high-k material,tandem structure, | en |
dc.relation.page | 52 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2014-08-13 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-103-1.pdf 目前未授權公開取用 | 4.3 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。