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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 呂學士 | |
dc.contributor.author | Fang-Ting Lee | en |
dc.contributor.author | 李昉亭 | zh_TW |
dc.date.accessioned | 2021-06-08T06:01:21Z | - |
dc.date.copyright | 2007-07-30 | |
dc.date.issued | 2007 | |
dc.date.submitted | 2007-07-27 | |
dc.identifier.citation | [2.1] S. Y. Liu, Analysis and Design of Phase-Locked Loops, class notes, Grad. Inst. of Electronics Engineering, National Taiwan University, spring 2006
[2.2] B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998. [2.3] D. Banerjee, PLL performance, simulation, and design, National Semiconductor, available on: http://webench.national.com/appinfo/wireless/files/deansbook4.pdf [2.4] F. Gardner, “Charge-pump phase-lock loops,” IEEE Trans. Communication, vol. 28, pp. 1849-1858, Nov. 1980 [2.5] R. E. Best, Phase-Locked Loops: Design, Simulation, and Applications, New York: McGraw-Hill, 2003 [2.6] T. S. Aytur and B. Razavi, “A 2-GHz, 6-mW BiCMOS Frequency Synthesizer,” IEEE J. Solid-State Circuits, vol. 30, pp.1457-1462, Dec. 1995 [2.7] C. Vaucher and D. Kasperkovitz, “A wide-band tuning system for fully integrated satellite receivers,” IEEE J. Solid-State Circuits, pp.987-997, July 1998. [2.8] J. Craninckx and M.S.J. Steyaert, “A 1.75GHz/3V dual-modulus divide -by-128/129 prescaler in 0.7-μm CMOS,” IEEE J. Solid-State Circuits, pp.890-897, July 1996. [2.9] B. Razavi, Design of Analog CMOS Integrated Circuits, New-York: McGraw-Hill, 2001. [2.10] Y. C. Yang, The design and application of CMOS fully-integrated PLL-based fractional-N frequency synthesizers, Ph.D Dissertation, Grad. Inst. of Electronics Engineering, National Taiwan University, Jul. 2007. [2.11] K. Shu, et al., “A 2.4-GHz Monolithic Fractional-N Frequency Synthesizer With Robust Phase-Switching Prescaler and Loop Capacitance Multiplier,” IEEE J. Solid-State Circuits, pp. 866-874, Jun. 2003. [2.12] D. Mijuskovic, M. J. Bayer, T. F. Chomicz, N. K. Garg, F. James, P. W. McEntarfer, and J. A. Porter, “Cell-based Fully Integrated CMOS Frequency Synthesizers,” IEEE J. Solid-State Circuits, pp. 271-279, Mar. 1994. [2.13] J. Craninckx and M. S. J. Steyaert, “A Fully Integrated CMOS DCS-1800 Frequency Synthesizer,” IEEE J. Solid-State Circuits, pp. 2054-2065, Dec. 1998. [2.14] W. Chen and J. Wu, “A 2-V 1.8-GHz BJT Phase-Locked Loop,” IEEE J. Solid-State Circuits, pp. 784-789, June 1999. [2.15] C. Lo and H. C. Luong, “A 1.5-V 900-MHz Monolithic CMOS Fast-Switching Frequency Synthesizer for Wireless Applications,” IEEE J. Solid-State Circuits, pp. 459–470, Apr. 2002. [2.16] Y. Koo, H. Huh, Y. Cho, J. Lee, J. Park, K. Lee, D. Jeong, and W. Kim, “A Fully Integrated CMOS Frequency Synthesizer With Charge-Averaging Charge Pump and Dual-Path Loop Filter for PCS- and Cellular-CDMA Wireless Systems,” IEEE J. Solid-State Circuits, pp. 536-542, May 2002. [2.17] F. M. Garner, “Charge-Pump Phase-Locked Loops,” IEEE Trans. on Communications, pp. 1849-1858, Nov. 1980. [2.18] National Semiconductor, An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLLs, Application Note 1001, Jul. 2001 ----------------------------------------------------------- [3.1] D. Mijuskovic, M. J. Bayer, T. F. Chomicz, N. K. Garg, F. James, P. W. McEntarfer, and J. A. Porter, “Cell-based fully integrated CMOS frequency synthesizers,” IEEE J. Solid-State Circuits, vol. 29, pp. 271-279, Mar. 1994. [3.2] J. Craninckx and M. S. J. Steyaert, “A fully integrated CMOS DCS-1800 frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 33, pp. 2054-2065, Dec. 1998. [3.3] W. Chen and J. Wu, “A 2-V 1.8-GHz BJT phase-locked loop,” IEEE J. Solid-State Circuits, vol. 34, pp. 784-789, June 1999. [3.4] C. Lo and H. C. Luong, “A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications,” IEEE J. Solid-State Circuits, vol. 37, pp. 459-470, Apr. 2002. [3.5] Y. Koo, H. Huh, Y. Cho, J. Lee, J. Park, K. Lee, D. Jeong, and W. Kim, “A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems,” IEEE J. Solid-State Circuits, vol. 37, pp. 536-542, May 2002. [3.6] S. Solis-Bustos, J. Silva-Martínez, F. Maloberti, and E. Sánchez-Sinencio, “A 60-dB dynamic range CMOS sixth-order 2.4-Hz low-pass filter for medical applications,” IEEE Trans. on Circuits and System-II: Analog and Digital Signal Processing, vol. 47, pp. 1391-1398, Dec. 2000. [3.7] K. Shu, E. Sánchez-Sinencio, J. Silva-Martínez and Sherif H. K. Embabi, “A 2.4-GHz Monolithic Fractional-N Frequency Synthesizer With Robust Phase-Switching Prescaler and Loop Capacitance Multiplier,” IEEE J. Solid-State Circuits, vol. 38, pp. 866-874, Jun. 2003. [3.8] E. Vittoz, “The design of high performance analog circuits on digital CMOS chips,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 657-665, June 1985. [3.9] E. Vittoz and J. Fellrath, “CMOS analog circuits based on weak inversion operation,” IEEE J. Solid-State Circuits, vol. SC-12, pp. 224-231, June 1977. [3.10] H. J. Oguey and D. Aebischer, “CMOS Current Reference Without Resistance,” IEEE J. Solid-State Circuits, vol. 32, pp. 1132-1315, Jul. 1997. [3.11] J. Craninckx and M. Steyaert, “A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors,” IEEE J. Solid-State Circuits, vol. 32, pp. 736-744, May 1997. [3.12] B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J. Solid-State Circuits, vol. 31, pp. 331-343, Mar. 1996. [3.13] W. S. T. Yan and H. C. Luong, “A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator,” IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 48, pp. 216-221, Feb. 2001. [3.14] B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998. [3.15] Y. Akazawa et al., “Low power 1 GHz frequency synthesizer LSI’s,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 115-121, Jan. 1983. [3.16] N.-H. Sheng et al., “A high-speed multimodulus HBT prescaler for frequency synthesizer applications,” IEEE J. Solid-State Circuits, vol. 26, pp. 1362–1367, Oct. 1991. [3.17] S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli and Z. Wang, “A family of low-power truly modular programmable dividers in standard 0.35-um CMOS technology,” IEEE J. Solid-State Circuits, vol. 31, pp. 1039-1045, Jul. 2000. [3.18] T. P. Kenny, T. A. D. Riley, N. M. Filiol and M. A. Copeland, “Design and realization of a digital delta-sigma modulator for fractional-n frequency synthesis,” IEEE J. Solid-State Circuits, vol. 48, pp. 510-521, Mar. 1999. [3.19] T. A. D. Riley, M. A. Copeland and T. A. Kwasniewski, “Delta-sigma modulation in fractional-n frequency synthesis,” IEEE J. Solid-State Circuits, vol. 28, pp. 553-559, May 1993. [3.20] W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked loops,” Proc. of IEEE International Symp. on Circuits and Systems, vol. 2, 1999, pp. 545-548. [3.21] M. El-Hage and F. Yuan, “Architectures and design considerations of CMOS charge pumps for phase-locked loops,” Canadian Conf. on Electrical and Computer Engineering, vol. 1, 2003, pp. 223-226. ----------------------------------------------------------- [4.1] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 717-724, May 1999. [4.2] R. L. Bunch and S. Raman, “Large-signal analysis of MOS varactors in CMOS –Gm LC VCOs,” IEEE J. Solid-State Circuits, vol. 38, pp. 1325-1332, Aug. 2003. [4.3] J. Craninckx and M. S. J. Steyaert, “A fully integrated CMOS DCS-1800 frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 33, pp. 2054-2065, Dec. 1998. [4.4] C. H. Wu, C. Y. Kuo and S. I. Liu, “Selective metal parallel shunting inductor and its VCO Application,” Symp. on VLSI Circuits, Dig. Tech. Papers, 2003, pp. 37-40. [4.5] L. Wiemer and R. H. Jansen, “Determination of coupling capacitance of unpasses, air bridges and crossings in MIC’s and MMIC’s,” Electron. Lett., vol. 23, pp. 344-346, Mar. 1987. [4.6] C. Cao and Kenneth K. O., “Millimeter-wave voltage-controlled oscillators in 0.13-um CMOS Technology,” IEEE J. Solid-State Circuits, vol. 41, pp. 1297-1304, Jun. 2006. ----------------------------------------------------------- [5.1] M. H. Perrott, T. L. Tewksbury III and C. G. Sodini, “A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK Modulation,” IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2060, Dec. 1997. [5.2] T. A. D. Riley and M. A. Copeland, “A simplified continuous phase modulator technique,” IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 41, pp. 321-328, May 1994. [5.3] R. A. Meyers and P. H. Waters, “Synthesizer review for pan-European digital cellular radio,” Proc. IEE VLSI Implementations for Second Generation Digital Cordless and Mobile Telecommunication Systems Colloq., 1990, pp. 8/1-8/8. [5.4] S. Heinen, K. Hadjizada, U. Matter, W. Geppert, V. Thomas, S. Weber, S. Beyer, J. Fenk and E. Matschke, “2.7V 2.5 GHz bipolar chipset for digital wireless communication,” Proc. IEEE Integrated Solid-State Circuits Conf., Feb. 1997, pp. 306-307. [5.5] K. C. P, C. H. Huang, C. J. Li and T. S. Horng, “High-performance frequency-hopping transmitters using two-point delta-sigma modulation,” Trans. on Microwave Theory and Techniques, vol. 52, pp. 2529-2535, Nov. 2004. [5.6] T. C. Lee, Advanced Analog Integrated Circuits, class notes, Grad. Inst. Of Electronics Engineering, National Taiwan University, spring 2006. ----------------------------------------------------------- [A.1] K. Shu and E. Sánchez-Sinencio, CMOS PLL Synthesizers: Analysis and Design, Springer, 2005. [A.2] A. Zanchi, C. Samori, S. Levantino, and A. Lacaita, “A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop,” IEEE J. Solid-State Circuits, vol. 36, pp. 611-619, Apr. 2001. [A.3] A. Zanchi, C. Samori, A. Lacaita, and S. Levantino, “Impact of AAC design on phase noise performance of VCOs,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 537-547, June 2001. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25061 | - |
dc.description.abstract | 近年來,以鎖相迴路為主的頻率合成器大量被使用在無線通訊系統中。由於整數型鎖相迴路本身有鎖定時間與頻率解析度的設計衝突,因此分數型頻率合成器較常被使用在無線應用中,因為它可以消除迴路頻寬與頻率解析度的設計衝突。
本論文的主題是利用標準的0.35微米CMOS製程來設計及實現三個分數型頻率合成器。電路實作的內容概要如下: 第一塊電路是一個運作於915 MHz的分數型頻率合成器。該頻率合成器適用於低功率及高整合度的應用。電路中所採用的容值倍增器可將小容值乘以某個倍數放大,如此一來即可用較小的容值來產生等效的大容值,有效減少迴路濾波器的晶片面積以利單晶片整合。為了降低功率消耗,該電路採用環狀震盪器作為壓控震盪器。 在第二塊電路實作中,我們實現一個可運作於315/433/868/915 MHz ISM頻帶的分數型頻率合成器。該電路中使用LC震盪器及三階的三角積分調變器來改善相位雜訊。量測結果顯示四個ISM操作頻段皆有涵蓋到,並有較低的相位雜訊。 在第三塊架構中,我們實現一個利用第四章分數型頻率合成器實現的高斯頻移鍵控調變器。直接對三角積分調變器的輸入端進行調變是個可輕易達成數位調變,並同時維持較低的相位雜訊的架構。另外,我們也使用雙點調變的機制,在壓控震盪器的輸入端增設一條具高通特性的調變路徑,以提升資料傳輸率,使其不被鎖相迴路的頻寬限制住。 | zh_TW |
dc.description.abstract | In recent years, PLL-based frequency synthesizers have been widely used in wireless communication systems. However, the integer-N PLLs suffer from several tradeoffs, such as the tradeoff between the tuning speed and the frequency resolution. In order to break the tie between the reference frequency and the step size, fractional-N synthesizers are mostly adopted in many communication applications.
This thesis presents the design and implementation of CMOS integrated fractional-N frequency synthesizers. Three fractional-N frequency synthesizers have been implemented and fabricated in standard 0.35-um CMOS process. The first chip is a 915-MHz fractional-N frequency synthesizer targeting the low power and high integration applications. This prototype achieves full integration by using capacitance multiplier to scale up a small capacitance by a desired factor. This technique effectively reduces the integrating capacitor in the loop filter, which is often an integration bottleneck of the PLL. A ring oscillator is also employed in order to save power consumption. The second chip is a fractional-N frequency synthesizer for 315/433/868/915 MHz ISM applications. The use of an LC VCO and a third-order delta-sigma modulator ensures the spectral purity. The measurement results indicate the entire coverage of the expected frequency bands, and the measured phase noise performs well. The third chip is a GFSK modulator using the fractional-N frequency synthesizer introduced in chapter 4. Directly modulating the input of the delta-sigma modulator allows digital frequency modulation to be easily accomplished while simultaneously achieve good noise performance. Moreover, the two-point modulation technique creates a second modulation path to inject the transmission signals into the second tuning port of the VCO. Using such technique, the maximum available data rate can exceed the PLL loop bandwidth. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T06:01:21Z (GMT). No. of bitstreams: 1 ntu-96-R94943054-1.pdf: 5175974 bytes, checksum: 786763b4b6e033994f6f9426f6c95f71 (MD5) Previous issue date: 2007 | en |
dc.description.tableofcontents | Table of Contents--------------------------------------------I
List of Figures---------------------------------------------IV List of Tables--------------------------------------------VIII Chapter 1 Introduction-----------------------------------1 1.1 Introduction------------------------------------------1 1.2 Overview of this Thesis-------------------------------2 Chapter 2 Fundamentals of Phase-Locked Loops-------------5 2.1 Basic PLL Operation-----------------------------------6 2.2 General Considerations--------------------------------8 2.2.1 Phase Noise / Jitter--------------------------------8 2.2.2 Spurs----------------------------------------------12 2.2.3 Lock Time------------------------------------------14 2.3 Building Blocks of Charge Pump PLL-------------------15 2.3.1 Voltage-Controlled Oscillator (VCO)----------------15 2.3.2 Frequency Divider----------------------------------17 2.3.3 Phase/Frequency Detector (PFD) and Charge Pump (CP)18 2.3.4 Loop Filter----------------------------------------24 2.4 Transfer Functions of PLL----------------------------26 2.5 Charge Pump PLL Design-------------------------------28 2.5.1 Second-Order PLL-----------------------------------29 2.5.2 Third-Order PLL------------------------------------31 2.5.3 Fourth-Order PLL-----------------------------------34 2.5.4 Transient Response of PLL--------------------------36 2.6 Phase Noise Analysis---------------------------------38 Chapter 3 A 915-MHz Fractional-N Frequency Synthesizer--43 3.1 Introduction-----------------------------------------43 3.2 Frequency Synthesizer Architecture-------------------44 3.3 Loop Filter with Capacitance Multiplier--------------46 3.3.1 Characteristics of the Second-Order Loop Filter----47 3.3.2 Design of Capacitance Multiplier-------------------48 3.3.3 Current Reference----------------------------------54 3.4 Ring Oscillator--------------------------------------57 3.4.1 Circuit Implementation-----------------------------57 3.4.2 Simulation Results and Layout----------------------60 3.5 Other Building Blocks of the Frequency Synthesizer---63 3.5.1 Divide-by-Two Divider------------------------------63 3.5.2 Truly Modular Programmable Divider-----------------65 3.5.3 Delta-Sigma Modulator------------------------------68 3.5.4 PFD/CP---------------------------------------------73 3.5.5 Serial Control Interface---------------------------78 3.6 Experimental Results---------------------------------79 3.6.1 Measurement Setup----------------------------------81 3.6.2 Experimental Results-------------------------------83 3.7 Summary----------------------------------------------88 Chapter 4 A Fractional-N Frequency Synthesizer for 315/433/868/915 MHz ISM Bands----------------------------93 4.1 Introduction-----------------------------------------93 4.2 Frequency Synthesizer Architecture-------------------94 4.3 LC VCO-----------------------------------------------96 4.3.1 Principles and Circuit Implementation of LC VCO----97 4.3.2 Design of Spiral Inductor-------------------------100 4.3.3 Layout and Simulation Results of LC VCO-----------104 4.4 Hardware-Reduced Delta-Sigma Modulator--------------107 4.5 Other Building Blocks of the Frequency Synthesizer--109 4.5.1 Divider-------------------------------------------109 4.5.2 PFD/CP and Loop Filer-----------------------------112 4.5.3 Three-Wire Control Interface----------------------113 4.6 Experimental Results--------------------------------114 4.6.1 Measurement Setup---------------------------------114 4.6.2 Experimental Results------------------------------118 4.7 Summary---------------------------------------------126 Chapter 5 A GFSK Modulator Using Fractional-N Frequency Synthesizer for Multiple ISM Bands----------------------129 5.1 Introduction----------------------------------------129 5.2 Frequency Modulation Schemes------------------------130 5.3 Two-Point Modulation Technique----------------------134 5.4 Circuit Implementation------------------------------137 5.4.1 Gaussian Filter-----------------------------------137 5.4.2 Digital-to-Analog Converter (DAC)-----------------139 5.5 Experimental Results--------------------------------142 5.5.1 Measurement Setup---------------------------------142 5.5.2 Experimental Results------------------------------146 5.6 Summary---------------------------------------------150 Chapter 6 Conclusion-----------------------------------153 Appendix Phase Noise and Spurs--------------------------157 | |
dc.language.iso | zh-TW | |
dc.title | 適用於315/433/868/915 MHz ISM頻帶之分數型頻率合成器 | zh_TW |
dc.title | A Fractional-N Frequency Synthesizer for 315/433/868/915 MHz ISM Bands | en |
dc.type | Thesis | |
dc.date.schoolyear | 95-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 孟慶宗,孫台平,李朝政,邱弘緯 | |
dc.subject.keyword | 鎖相迴路,頻率合成器,射頻,積體電路,三角積分調變器, | zh_TW |
dc.subject.keyword | PLL,phase-locked loop,frequency synthesizer,delta-sigma,GFSK,transmitter,ISM,RF,radio-frequency, | en |
dc.relation.page | 159 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2007-07-30 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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